FULL_SYS |

2012.09.02.21:14:51 | Datasheet

Overview

clk_0 | FULL_SYS
| epcs_flash_controller
| dclk
| sce
| sdo
| data0
| tse_mac
| rgmii_in
| rgmii_out
| rx_control
| tx_control
| tx_clk
| rx_clk
| set_10
| set_1000
| ena_10
| eth_mode
| mdio_out
| mdio_oen
| mdio_in
| mdc
| led_pio
| out_port
| in_port

Processor
CPU Nios II 12.0
All Components
CPU altera_nios2_qsys 12.0
RAM altera_avalon_onchip_memory2 12.0
epcs_flash_controller altera_avalon_epcs_flash_controller 12.0
DDR2 altmemddr2 12.0
jtag_uart altera_avalon_jtag_uart 12.0
descriptor_memory altera_avalon_onchip_memory2 12.0
sgdma_tx altera_avalon_sgdma 12.0
sgdma_rx altera_avalon_sgdma 12.0
tse_mac triple_speed_ethernet 12.0
led_pio altera_avalon_pio 12.0
button_pio altera_avalon_pio 12.0
ext_flash altera_generic_tristate_controller 12.0
sys_timer altera_avalon_timer 12.0
sd_card sd_controller 1.0
Memory Map

| CPU | sgdma_tx | sgdma_rx
data_master | instruction_master | descriptor_read | descriptor_write | m_read | descriptor_read | descriptor_write | m_write
CPU |  |  |  |  |  |  |  |
jtag_debug_module | 0x00002000 | 0x00002000 |  |  |  |  |  |
RAM |  |  |  |  |  |  |  |
s1 | 0x00008000 | 0x00008000 |  |  |  |  |  |
epcs_flash_controller |  |  |  |  |  |  |  |
epcs_control_port | 0x00000000 | 0x00000000 |  |  |  |  |  |
DDR2 |  |  |  |  |  |  |  |
s1 | 0x08000000 | 0x08000000 |  |  | 0x08000000 |  |  | 0x08000000
jtag_uart |  |  |  |  |  |  |  |
avalon_jtag_slave | 0x000030c0 |  |  |  |  |  |  |
descriptor_memory |  |  |  |  |  |  |  |
s1 | 0x00001000 |  | 0x00001000 | 0x00001000 |  | 0x00001000 | 0x00001000 |
sgdma_tx |  |  |  |  |  |  |  |
csr | 0x00003040 |  |  |  |  |  |  |
sgdma_rx |  |  |  |  |  |  |  |
csr | 0x00003000 |  |  |  |  |  |  |
tse_mac |  |  |  |  |  |  |  |
control_port | 0x00002800 |  |  |  |  |  |  |
led_pio |  |  |  |  |  |  |  |
s1 | 0x000030a0 |  |  |  |  |  |  |
button_pio |  |  |  |  |  |  |  |
s1 | 0x000030b0 |  |  |  |  |  |  |
ext_flash |  |  |  |  |  |  |  |
uas | 0x02000000 | 0x02000000 |  |  |  |  |  |
sys_timer |  |  |  |  |  |  |  |
s1 | 0x00003080 |  |  |  |  |  |  |
sd_card |  |  |  |  |  |  |  |
avalon_slave | 0x00002c00 |  |  |  |  |  |  |

## clk_0

clock_source v12.0

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## CPU

altera_nios2_qsys v12.0

DDR2 | sysclk | CPU
clk
clk_0 | clk_reset
reset_n
|  | jtag_debug_module_reset | RAM
|  | reset1
|  | data_master
|  | s1
|  | instruction_master
|  | s1
|  | jtag_debug_module_reset | epcs_flash_controller
|  | reset
|  | instruction_master
|  | epcs_control_port
|  | data_master
|  | epcs_control_port
|  | d_irq
|  | irq
|  | data_master | DDR2
|  | s1
|  | instruction_master
|  | s1
|  | jtag_debug_module_reset
|  | soft_reset_n
|  | jtag_debug_module_reset | jtag_uart
|  | reset
|  | data_master
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | descriptor_memory
|  | s1
|  | jtag_debug_module_reset
|  | reset1
|  | data_master | tse_mac
|  | control_port
|  | jtag_debug_module_reset
|  | reset_connection
|  | data_master | sgdma_rx
|  | csr
|  | d_irq
|  | csr_irq
|  | jtag_debug_module_reset
|  | reset
|  | data_master | sgdma_tx
|  | csr
|  | d_irq
|  | csr_irq
|  | jtag_debug_module_reset
|  | reset
|  | jtag_debug_module_reset | led_pio
|  | reset
|  | data_master
|  | s1
|  | data_master | ext_flash
|  | uas
|  | instruction_master
|  | uas
|  | jtag_debug_module_reset
|  | reset
|  | jtag_debug_module_reset | button_pio
|  | reset
|  | data_master
|  | s1
|  | d_irq
|  | irq
|  | jtag_debug_module_reset | ext_flash_bridge
|  | reset
|  | jtag_debug_module_reset | sys_timer
|  | reset
|  | data_master
|  | s1
|  | d_irq
|  | irq
|  | jtag_debug_module_reset | sd_card
|  | clock_reset
|  | data_master
|  | avalon_slave

## Parameters

setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
muldiv_divider | false
mpu_useLimit | false
mpu_enabled | false
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
manuallyAssignCpuID | true
debug_triggerArming | true
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
dcache_omitDataMaster | false
cpuReset | false
is_hardcopy_compatible | false
setting_shadowRegisterSets | 0
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mmu_TLBMissExcOffset | 0
debug_jtagInstanceID | 0
resetOffset | 0
exceptionOffset | 32
cpuID | 0
cpuID_stored | 0
breakOffset | 32
userDefinedSettings |
resetSlave | epcs_flash_controller.epcs_control_port
mmu_TLBMissExcSlave |
exceptionSlave | RAM.s1
breakSlave | CPU.jtag_debug_module
setting_perfCounterWidth | 32
setting_interruptControllerType | Internal
setting_branchPredictionType | Automatic
setting_bhtPtrSz | 8
muldiv_multiplierType | EmbeddedMulFast
mpu_minInstRegionSize | 12
mpu_minDataRegionSize | 12
mmu_uitlbNumEntries | 4
mmu_udtlbNumEntries | 6
mmu_tlbPtrSz | 7
mmu_tlbNumWays | 16
mmu_processIDNumBits | 8
impl | Fast
icache_size | 4096
icache_ramBlockType | Automatic
icache_numTCIM | 0
icache_burstType | None
dcache_bursts | false
debug_level | Level1
debug_OCIOnchipTrace | _128
dcache_size | 2048
dcache_ramBlockType | Automatic
dcache_numTCDM | 0
dcache_lineSize | 32
resetAbsoluteAddr | 0
exceptionAbsoluteAddr | 32800
breakAbsoluteAddr | 8224
mmu_TLBMissExcAbsAddr | 0
instAddrWidth | 28
dataAddrWidth | 28
tightlyCoupledDataMaster0AddrWidth | 1
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster3AddrWidth | 1
instSlaveMapParam | <address-map><slave name='epcs_flash_controller.epcs_control_port' start='0x0' end='0x800' /><slave name='CPU.jtag_debug_module' start='0x2000' end='0x2800' /><slave name='RAM.s1' start='0x8000' end='0x9000' /><slave name='ext_flash.uas' start='0x2000000' end='0x3000000' /><slave name='DDR2.s1' start='0x8000000' end='0xC000000' /></address-map>
dataSlaveMapParam | <address-map><slave name='epcs_flash_controller.epcs_control_port' start='0x0' end='0x800' /><slave name='descriptor_memory.s1' start='0x1000' end='0x2000' /><slave name='CPU.jtag_debug_module' start='0x2000' end='0x2800' /><slave name='tse_mac.control_port' start='0x2800' end='0x2C00' /><slave name='sd_card.avalon_slave' start='0x2C00' end='0x3000' /><slave name='sgdma_rx.csr' start='0x3000' end='0x3040' /><slave name='sgdma_tx.csr' start='0x3040' end='0x3080' /><slave name='sys_timer.s1' start='0x3080' end='0x30A0' /><slave name='led_pio.s1' start='0x30A0' end='0x30B0' /><slave name='button_pio.s1' start='0x30B0' end='0x30C0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x30C0' end='0x30C8' /><slave name='RAM.s1' start='0x8000' end='0x9000' /><slave name='ext_flash.uas' start='0x2000000' end='0x3000000' /><slave name='DDR2.s1' start='0x8000000' end='0xC000000' /></address-map>
clockFrequency | 75000000
deviceFamilyName | STINGRAY
internalIrqMaskSystemInfo | 63
customInstSlavesSystemInfo | <info/>
deviceFeaturesSystemInfo | NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 1 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster3MapParam |
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster3MapParam |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIG_ENDIAN | 0
BREAK_ADDR | 0x00002020
CPU_FREQ | 75000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "fast"
DATA_ADDR_WIDTH | 28
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
EXCEPTION_ADDR | 0x00008020
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INITDA_SUPPORTED |
INST_ADDR_WIDTH | 28
NUM_OF_SHADOW_REG_SETS | 0
RESET_ADDR | 0x00000000

## RAM

altera_avalon_onchip_memory2 v12.0

DDR2 | sysclk | RAM
clk1
clk_0 | clk_reset
reset1
CPU | jtag_debug_module_reset
reset1
data_master
s1
instruction_master
s1

## Parameters

allowInSystemMemoryContentEditor | false
autoInitializationFileName | FULL_SYS_RAM
blockType | AUTO
dataWidth | 32
deviceFamily | STINGRAY
dualPort | false
initMemContent | true
initializationFileName | RAM
instanceID | NONE
memorySize | 4096
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
generateLegacySim | false

## Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "RAM"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SINGLE_CLOCK_OP | 0
SIZE_VALUE | 4096u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## epcs_flash_controller

altera_avalon_epcs_flash_controller v12.0

DDR2 | sysclk | epcs_flash_controller
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
instruction_master
epcs_control_port
data_master
epcs_control_port
d_irq
irq

## Parameters

autoSelectASMIAtom | true
clockRate | 75000000
deviceFamilyString | STINGRAY
useASMIAtom | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

REGISTER_OFFSET | 1024

## DDR2

altmemddr2 v12.0

clk_0 | clk | DDR2
refclk
clk_reset
global_reset_n
clk_reset
soft_reset_n
CPU | data_master
s1
instruction_master
s1
jtag_debug_module_reset
soft_reset_n
sgdma_tx | m_read
s1
sgdma_rx | m_write
s1
|  | sysclk | CPU
|  | clk
|  | sysclk | RAM
|  | clk1
|  | sysclk | epcs_flash_controller
|  | clk
|  | sysclk | jtag_uart
|  | clk
|  | sysclk | descriptor_memory
|  | clk1
|  | sysclk | sgdma_tx
|  | clk
|  | sysclk | sgdma_rx
|  | clk
|  | sysclk | tse_mac
|  | receive_clock_connection
|  | sysclk
|  | transmit_clock_connection
|  | sysclk
|  | control_port_clock_connection
|  | sysclk | led_pio
|  | clk
|  | sysclk | button_pio
|  | clk
|  | sysclk | ext_flash
|  | clk
|  | sysclk | ext_flash_bridge
|  | clk
|  | sysclk | sys_timer
|  | clk
|  | sysclk | sd_card
|  | clock

## Parameters

pipeline_commands | false
debug_en | false
export_debug_port | false
use_generated_memory_model | true
dedicated_memory_clk_phase_label | Dedicated memory clock phase:
mem_if_clk_mhz | 150.0
quartus_project_exists | false
local_if_drate | Half
enable_v72_rsu | false
local_if_clk_mhz_label | 75.0
new_variant | true
mem_if_memtype | DDR2 SDRAM
pll_ref_clk_mhz | 50.0
mem_if_clk_ps_label | (6667 ps)
family | Cyclone IV GX
project_family | Cyclone IV GX
speed_grade | 8
dedicated_memory_clk_phase | 0
pll_ref_clk_ps_label | (20000 ps)
avalon_burst_length | 1
mem_if_clk_pair_count | 1
mem_if_cs_per_dimm | 1
pre_latency_label | Fix read latency at:
dedicated_memory_clk_en | false
mirror_addressing | 0
mem_if_bankaddr_width | 3
register_control_word_9 | 0000
mem_if_rowaddr_width | 13
mem_dyn_deskew_en | false
post_latency_label | cycles (0 cycles=minimum latency, non-deterministic)
mem_if_dm_pins_en | Yes
local_if_dwidth_label | 64
register_control_word_7 | 0000
register_control_word_8 | 0000
mem_if_preset | Custom (MT47H32M16HR-25E)
mem_if_pchaddr_bit | 10
WIDTH_RATIO | 4
vendor | Micron
register_control_word_3 | 0000
register_control_word_4 | 0000
chip_or_dimm | Discrete Device
register_control_word_5 | 0000
register_control_word_6 | 0000
mem_fmax | 267.0
register_control_word_0 | 0000
register_control_word_size | 4
register_control_word_1 | 0000
register_control_word_2 | 0000
register_control_word_11 | 0000
register_control_word_10 | 0000
mem_if_cs_width | 1
mem_if_preset_rlat | 0
mem_if_cs_per_rank | 1
fast_simulation_en | FAST
register_control_word_15 | 0000
register_control_word_14 | 0000
mem_if_dwidth | 16
mem_if_dq_per_dqs | 8
mem_if_coladdr_width | 9
register_control_word_13 | 0000
register_control_word_12 | 0000
mem_tiha_ps | 500
mem_tdsh_ck | 0.2
mem_if_trfc_ns | 75.0
mem_tqh_ck | 0.36
mem_tisa_ps | 500
mem_tdss_ck | 0.2
mem_trtp_ns | 8.8
mem_if_tinit_us | 200.0
mem_if_trcd_ns | 15.0
mem_if_twtr_ck | 2
mem_trrd_ns | 10.0
mem_tdqss_ck | 0.25
mem_tqhs_ps | 400
mem_tdsa_ps | 345
mem_tac_ps | 500
mem_tdha_ps | 285
mem_if_tras_ns | 40.0
mem_if_twr_ns | 15.0
mem_tdqsck_ps | 450
mem_if_trp_ns | 15.0
mem_tdqsq_ps | 300
mem_if_tmrd_ns | 7.5
mem_tfaw_ns | 50.0
mem_if_trefi_us | 7.8
mem_tcl_40_fmax | 267.0
mem_odt | Disabled
mp_WLH_percent | 0.6
mem_drv_str | Normal
mp_DH_percent | 0.5
input_period | 0
mp_QH_percent | 0.5
mp_QHS_percent | 0.5
mem_tcl_30_fmax | 200.0
ac_clk_select | 90
mp_DQSQ_percent | 0.65
mp_DS_percent | 0.6
pll_reconfig_ports_en | false
mem_btype | Sequential
mp_IS_percent | 0.7
mem_tcl | 5.0
mp_DQSS_percent | 0.5
export_bank_info | false
mp_DSS_percent | 0.6
mem_dll_en | Yes
ac_phase | 90
mem_if_oct_en | false
mem_tcl_60_fmax | 267.0
mp_DSH_percent | 0.6
mem_if_dqsn_en | false
enable_mp_calibration | true
mp_IH_percent | 0.6
mem_tcl_15_fmax | 533.0
dll_external | false
mem_bl | 8
mp_WLS_percent | 0.7
mem_tcl_50_fmax | 267.0
mp_DQSCK_percent | 0.5
mem_tcl_25_fmax | 533.0
mem_tcl_20_fmax | 533.0
cfg_reorder_data | true
ctl_ecc_en | false
ctl_hrb_en | false
ref_clk_source | clk_0
cfg_data_reordering_type | INTER_BANK
ctl_powerdn_en | false
multicast_wr_en | false
auto_powerdn_cycles | 0
ctl_self_refresh_en | false
cfg_starve_limit | 10
shared_sys_clk_source |
ctl_latency | 0
tool_context | SOPC_BUILDER
mem_addr_mapping | CHIP_ROW_BANK_COL
burst_merge_en | false
user_refresh_en | false
qsys_mode | true
clk_source_sharing_en | false
ctl_lookahead_depth | 4
ctl_autopch_en | false
ctl_dynamic_bank_allocation | false
ctl_dynamic_bank_num | 4
local_if_type_avalon | true
csr_en | false
ctl_auto_correct_en | false
auto_powerdn_en | false
phy_if_type_afi | true
controller_type | ngv110_ctl
max_local_size | 4
mem_srtr | Normal
mem_mpr_loc | Predefined Pattern
dss_tinit_rst_us | 200.0
mem_tcl_90_fmax | 400.0
mem_rtt_wr | Dynamic ODT off
mem_tcl_100_fmax | 400.0
mem_pasr | Full Array
mem_asrm | Manual SR Reference (SRT)
mem_mpr_oper | Predefined Pattern
mem_tcl_80_fmax | 400.0
mem_drv_impedance | RZQ/7
mem_rtt_nom | ODT Disabled
mem_tcl_70_fmax | 400.0
mem_wtcl | 5.0
mem_dll_pch | Fast Exit
mem_atcl | Disabled
board_settings_valid | true
t_IH | 0.5
board_intra_DQS_group_skew | 0.02
isi_DQS | 0.0
addr_cmd_slew_rate | 1.0
board_tpd_inter_DIMM | 0.05
board_addresscmd_CK_skew | 0.0
t_DS_calculated | 0.350
isi_addresscmd_hold | 0.0
t_IS | 0.5
restore_default_toggle | false
dqs_dqsn_slew_rate | 2.0
dq_slew_rate | 1.0
board_inter_DQS_group_skew | 0.02
isi_addresscmd_setup | 0.0
board_minCK_DQS_skew | -0.01
t_IS_calculated | 0.500
num_slots_or_devices | 1
board_maxCK_DQS_skew | 0.01
board_skew_ps | 20
t_DH | 0.35
ck_ckn_slew_rate | 2.0
isi_DQ | 0.0
t_IH_calculated | 0.500
t_DH_calculated | 0.350
t_DS | 0.35
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## jtag_uart

altera_avalon_jtag_uart v12.0

DDR2 | sysclk | jtag_uart
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
data_master
avalon_jtag_slave
d_irq
irq

## Parameters

allowMultipleConnections | false
avalonSpec | 2.0
hubInstanceID | 0
legacySignalAllow | false
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## descriptor_memory

altera_avalon_onchip_memory2 v12.0

DDR2 | sysclk | descriptor_memory
clk1
CPU | data_master
s1
jtag_debug_module_reset
reset1
clk_0 | clk_reset
reset1
sgdma_rx | descriptor_read
s1
descriptor_write
s1
sgdma_tx | descriptor_read
s1
descriptor_write
s1

## Parameters

allowInSystemMemoryContentEditor | false
autoInitializationFileName | FULL_SYS_descriptor_memory
blockType | AUTO
dataWidth | 32
deviceFamily | STINGRAY
dualPort | false
initMemContent | true
initializationFileName | descriptor_memory
instanceID | NONE
memorySize | 4096
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
generateLegacySim | false

## Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "descriptor_memory"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SINGLE_CLOCK_OP | 0
SIZE_VALUE | 4096u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## sgdma_tx

altera_avalon_sgdma v12.0

CPU | data_master | sgdma_tx
csr
d_irq
csr_irq
jtag_debug_module_reset
reset
DDR2 | sysclk
clk
clk_0 | clk_reset
reset
|  | out | tse_mac
|  | transmit
|  | descriptor_read | descriptor_memory
|  | s1
|  | descriptor_write
|  | s1
|  | m_read | DDR2
|  | s1

## Parameters

actualDataTransferFIFODepth | 64
addressWidth | 32
alwaysDoMaxBurst | true
avalonMMByteReorderMode | 0
dataTransferFIFODepth | 2
deviceFamilyString | STINGRAY
enableBurstTransfers | false
enableDescriptorReadMasterBurst | false
enableUnalignedTransfers | false
internalFIFODepth | 2
readBlockDataWidth | 32
readBurstcountWidth | 4
sinkErrorWidth | 0
sourceErrorWidth | 1
transferMode | MEMORY_TO_STREAM
writeBurstcountWidth | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

READ_BLOCK_DATA_WIDTH | 32
WRITE_BLOCK_DATA_WIDTH | 32
STREAM_DATA_WIDTH | 32
ADDRESS_WIDTH | 32
HAS_READ_BLOCK | 1
HAS_WRITE_BLOCK | 0
READ_BURSTCOUNT_WIDTH | 4
WRITE_BURSTCOUNT_WIDTH | 4
BURST_TRANSFER | 0
ALWAYS_DO_MAX_BURST | 1
DESCRIPTOR_READ_BURST | 0
UNALIGNED_TRANSFER | 0
CONTROL_SLAVE_DATA_WIDTH | 32
CONTROL_SLAVE_ADDRESS_WIDTH | 4
DESC_DATA_WIDTH | 32
CHAIN_WRITEBACK_DATA_WIDTH | 32
STATUS_TOKEN_DATA_WIDTH | 24
BYTES_TO_TRANSFER_DATA_WIDTH | 16
BURST_DATA_WIDTH | 8
CONTROL_DATA_WIDTH | 8
ATLANTIC_CHANNEL_DATA_WIDTH | 4
COMMAND_FIFO_DATA_WIDTH | 104
AVALON_MM_BYTE_REORDER_MODE | 0
SYMBOLS_PER_BEAT | 4
IN_ERROR_WIDTH | 0
OUT_ERROR_WIDTH | 1

## sgdma_rx

altera_avalon_sgdma v12.0

tse_mac | receive | sgdma_rx
in
CPU | data_master
csr
d_irq
csr_irq
jtag_debug_module_reset
reset
DDR2 | sysclk
clk
clk_0 | clk_reset
reset
|  | descriptor_read | descriptor_memory
|  | s1
|  | descriptor_write
|  | s1
|  | m_write | DDR2
|  | s1

## Parameters

actualDataTransferFIFODepth | 64
addressWidth | 32
alwaysDoMaxBurst | true
avalonMMByteReorderMode | 0
dataTransferFIFODepth | 2
deviceFamilyString | STINGRAY
enableBurstTransfers | false
enableDescriptorReadMasterBurst | false
enableUnalignedTransfers | false
internalFIFODepth | 2
readBlockDataWidth | 32
readBurstcountWidth | 4
sinkErrorWidth | 6
sourceErrorWidth | 0
transferMode | STREAM_TO_MEMORY
writeBurstcountWidth | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

READ_BLOCK_DATA_WIDTH | 32
WRITE_BLOCK_DATA_WIDTH | 32
STREAM_DATA_WIDTH | 32
ADDRESS_WIDTH | 32
HAS_READ_BLOCK | 0
HAS_WRITE_BLOCK | 1
READ_BURSTCOUNT_WIDTH | 4
WRITE_BURSTCOUNT_WIDTH | 4
BURST_TRANSFER | 0
ALWAYS_DO_MAX_BURST | 1
DESCRIPTOR_READ_BURST | 0
UNALIGNED_TRANSFER | 0
CONTROL_SLAVE_DATA_WIDTH | 32
CONTROL_SLAVE_ADDRESS_WIDTH | 4
DESC_DATA_WIDTH | 32
CHAIN_WRITEBACK_DATA_WIDTH | 32
STATUS_TOKEN_DATA_WIDTH | 24
BYTES_TO_TRANSFER_DATA_WIDTH | 16
BURST_DATA_WIDTH | 8
CONTROL_DATA_WIDTH | 8
ATLANTIC_CHANNEL_DATA_WIDTH | 4
COMMAND_FIFO_DATA_WIDTH | 104
AVALON_MM_BYTE_REORDER_MODE | 0
SYMBOLS_PER_BEAT | 4
IN_ERROR_WIDTH | 6
OUT_ERROR_WIDTH | 0

## tse_mac

triple_speed_ethernet v12.0

sgdma_tx | out | tse_mac
transmit
CPU | data_master
control_port
jtag_debug_module_reset
reset_connection
DDR2 | sysclk
receive_clock_connection
sysclk
transmit_clock_connection
sysclk
control_port_clock_connection
clk_0 | clk_reset
reset_connection
|  | receive | sgdma_rx
|  | in

## Parameters

atlanticSinkClockRate | 0
atlanticSinkClockSource | unassigned
atlanticSourceClockRate | 0
atlanticSourceClockSource | unassigned
avalonSlaveClockRate | 0
avalonSlaveClockSource | unassigned
avalonStNeighbours | unassigned=unassigned
channel_count | 1
core_variation | MAC_ONLY
core_version | 3072
crc32check16bit | 0
crc32dwidth | 8
crc32gendelay | 6
crc32s1l2_extern | false
cust_version | 0
dataBitsPerSymbol | 8
dev_version | 3072
deviceFamily | STINGRAY
deviceFamilyName | STINGRAY
eg_addr | 11
eg_fifo | 2048
ena_hash | false
enable_alt_reconfig | false
enable_clk_sharing | false
enable_ena | 32
enable_fifoless | false
enable_gmii_loopback | false
enable_hd_logic | true
enable_mac_flow_ctrl | true
enable_mac_txaddr_set | true
enable_mac_vlan | false
enable_maclite | false
enable_magic_detect | true
enable_multi_channel | false
enable_pkt_class | true
enable_pma | false
enable_ptp_1step | false
enable_reg_sharing | false
enable_sgmii | false
enable_shift16 | true
enable_sup_addr | false
enable_timestamping | false
enable_use_internal_fifo | true
export_calblkclk | false
export_pwrdn | false
ext_stat_cnt_ena | false
gigeAdvanceMode | true
ifGMII | RGMII
ifPCSuseEmbeddedSerdes | false
ing_addr | 11
ing_fifo | 2048
insert_ta | true
maclite_gige | false
max_channels | 1
mdio_clk_div | 40
phy_identifier | 0
ramType | AUTO
reset_level | 1
sopcSystemTopLevelName | FULL_SYS
starting_channel_number | 0
stat_cnt_ena | true
timingAdapterName | timingAdapter
toolContext | SOPC_BUILDER
transceiver_type | GXB
tstamp_fp_width | 4
uiEgFIFOSize | 2048 x 32 Bits
uiHostClockFrequency | 0
uiIngFIFOSize | 2048 x 32 Bits
uiMACFIFO | false
uiMACOptions | false
uiMDIOFreq | 0.0 MHz
uiMIIInterfaceOptions | false
uiPCSInterface | false
uiPCSInterfaceOptions | false
useLvds | false
useMAC | true
useMDIO | true
usePCS | false
use_sync_reset | true
generateLegacySim | false

## Software Assignments

UNASSIGNED | "unassigned"
TRANSMIT_FIFO_DEPTH | 2048
RECEIVE_FIFO_DEPTH | 2048
FIFO_WIDTH | 32
ENABLE_MACLITE | 0
MACLITE_GIGE | 0
RGMII | 1
USE_MDIO | 1
NUMBER_OF_CHANNEL | 1
NUMBER_OF_MAC_MDIO_SHARED | 1
IS_MULTICHANNEL_MAC | 0
MDIO_SHARED | 0
REGISTER_SHARED | 0
PCS | 0
PCS_SGMII | 0
PCS_ID | 0u

## led_pio

altera_avalon_pio v12.0

DDR2 | sysclk | led_pio
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
data_master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 75000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 75000000u

## button_pio

altera_avalon_pio v12.0

DDR2 | sysclk | button_pio
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
data_master
s1
d_irq
irq

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 75000000
direction | Input
edgeType | RISING
generateIRQ | true
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "LEVEL"
FREQ | 75000000u

## ext_flash

altera_generic_tristate_controller v12.0

CPU | data_master | ext_flash
uas
instruction_master
uas
jtag_debug_module_reset
reset
DDR2 | sysclk
clk
clk_0 | clk_reset
reset
|  | tcm | ext_flash_bridge
|  | tcs

## Parameters

TCM_ADDRESS_W | 24
TCM_DATA_W | 16
TCM_BYTEENABLE_W | 2
TCM_READ_WAIT | 100
TCM_WRITE_WAIT | 100
TCM_SETUP_WAIT | 60
TCM_DATA_HOLD | 20
TCM_MAX_PENDING_READ_TRANSACTIONS | 3
TCM_TURNAROUND_TIME | 2
TCM_TIMING_UNITS | 0
TCM_READLATENCY | 2
TCM_SYMBOLS_PER_WORD | 2
USE_READDATA | 1
USE_WRITEDATA | 1
USE_READ | 1
USE_WRITE | 1
USE_BEGINTRANSFER | 0
USE_BYTEENABLE | 0
USE_CHIPSELECT | 1
USE_LOCK | 0
USE_ADDRESS | 1
USE_WAITREQUEST | 0
USE_WRITEBYTEENABLE | 0
USE_OUTPUTENABLE | 0
USE_RESETREQUEST | 0
USE_IRQ | 0
USE_RESET_OUTPUT | 0
ACTIVE_LOW_READ | 1
ACTIVE_LOW_LOCK | 0
ACTIVE_LOW_WRITE | 1
ACTIVE_LOW_CHIPSELECT | 1
ACTIVE_LOW_BYTEENABLE | 0
ACTIVE_LOW_OUTPUTENABLE | 0
ACTIVE_LOW_WRITEBYTEENABLE | 0
ACTIVE_LOW_WAITREQUEST | 0
ACTIVE_LOW_BEGINTRANSFER | 0
ACTIVE_LOW_RESETREQUEST | 0
ACTIVE_LOW_IRQ | 0
ACTIVE_LOW_RESET_OUTPUT | 0
CHIPSELECT_THROUGH_READLATENCY | 0
IS_MEMORY_DEVICE | 1
MODULE_ASSIGNMENT_KEYS | embeddedsw.configuration.hwClassnameDriverSupportList,embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR
MODULE_ASSIGNMENT_VALUES | altera_avalon_lan91c111:altera_avalon_cfi_flash,altera_avalon_cfi_flash,60,100,20,ns,16777216u,16,1,1,1,1,SIM_DIR,APP_DIR
INTERFACE_ASSIGNMENT_KEYS | embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage
INTERFACE_ASSIGNMENT_VALUES | 1,1,1
CLOCK_RATE | 75000000
AUTO_CLK_CLOCK_DOMAIN | 2
AUTO_CLK_RESET_DOMAIN | 2
AUTO_TRISTATECONDUIT_MASTERS |
AUTO_DEVICE_FAMILY | STINGRAY
deviceFamily | Cyclone IV GX
generateLegacySim | false

## Software Assignments

HOLD_VALUE | 20
SETUP_VALUE | 60
SIZE | 16777216u
TIMING_UNITS | ns
WAIT_VALUE | 100

## ext_flash_bridge

altera_tristate_conduit_bridge v12.0

DDR2 | sysclk | ext_flash_bridge
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
ext_flash | tcm
tcs

## Parameters

INTERFACE_INFO | <info><slave name="tcs"><master name="ext_flash.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="24" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="data" width="16" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /></master></slave></info>
AUTO_CLK_CLOCK_RATE | 75000000
AUTO_DEVICE_FAMILY | STINGRAY
deviceFamily | Cyclone IV GX
generateLegacySim | false

## Software Assignments

(none)

## sys_timer

altera_avalon_timer v12.0

DDR2 | sysclk | sys_timer
clk
clk_0 | clk_reset
reset
CPU | jtag_debug_module_reset
reset
data_master
s1
d_irq
irq

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 75000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 75000000u
LOAD_VALUE | 74999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## sd_card

sd_controller v1.0

DDR2 | sysclk | sd_card
clock
clk_0 | clk_reset
clock_reset
CPU | jtag_debug_module_reset
clock_reset
data_master
avalon_slave

## Parameters

IDLE | 0
SHIFT_OUT_CMD | 1
WAIT_FOR_RSP_START | 2
SHIFT_IN_CMD_RSP | 3
WAIT_FOR_DATA_START | 4
SHIFT_IN_DATA | 5
SHIFT_IN_CRC16 | 6
SHIFT_OUT_DATA_TOKEN | 7
SHIFT_OUT_DATA | 8
SHIFT_OUT_CRC16 | 9
SHIFT_IN_DATA_RSP | 10
DATA_BUSY | 11
ERROR_STATE | 12
WAIT | 13
AUTO_CLOCK_CLOCK_RATE | 75000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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