<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="Default">
  <columns>
   <connections preferredWidth="335" />
   <irq preferredWidth="34" />
   <name preferredWidth="216" />
  </columns>
 </systemtable>
 <clocktable>
  <columns>
   <clockname preferredWidth="364" />
   <clocksource preferredWidth="362" />
   <frequency preferredWidth="344" />
  </columns>
 </clocktable>
 <window width="1366" height="737" x="0" y="0" />
 <library
   expandedCategories="Library,Project,Library/Verification,Library/Verification/Simulation,Library/Embedded Processors" />
 <hdlexample language="VERILOG" />
</preferences>
