#Core: FULL_SYS_DDR2_phy - Instance: inst7|ddr2|FULL_SYS_DDR2_controller_phy_inst|FULL_SYS_DDR2_phy_inst
#Path, Setup Margin, Hold Margin
"Address Command (Slow 1200mV 85C Model)",3.223,1.422
"DQS vs CK (Slow 1200mV 85C Model)",1.163,1.277
"Half Rate Address/Command (Slow 1200mV 85C Model)",9.837,1.390
"Mimic (Slow 1200mV 85C Model)",-0.081,
"Phy (Slow 1200mV 85C Model)",-0.081,0.432
"Phy Reset (Slow 1200mV 85C Model)",3.145,1.137
"Read Capture (Slow 1200mV 85C Model)",0.251,0.325
"Write (Slow 1200mV 85C Model)",0.276,0.683
 
"Address Command (Slow 1200mV 0C Model)",3.385,1.349
"DQS vs CK (Slow 1200mV 0C Model)",1.193,1.290
"Half Rate Address/Command (Slow 1200mV 0C Model)",9.998,1.317
"Mimic (Slow 1200mV 0C Model)",-0.140,
"Phy (Slow 1200mV 0C Model)",-0.140,0.400
"Phy Reset (Slow 1200mV 0C Model)",3.340,1.038
"Read Capture (Slow 1200mV 0C Model)",0.169,0.244
"Write (Slow 1200mV 0C Model)",0.300,0.710
 
"Address Command (Fast 1200mV 0C Model)",3.826,1.250
"DQS vs CK (Fast 1200mV 0C Model)",1.382,1.408
"Half Rate Address/Command (Fast 1200mV 0C Model)",10.440,1.218
"Mimic (Fast 1200mV 0C Model)",1.321,
"Phy (Fast 1200mV 0C Model)",1.321,0.152
"Phy Reset (Fast 1200mV 0C Model)",4.149,0.484
"Read Capture (Fast 1200mV 0C Model)",0.598,0.672
"Write (Fast 1200mV 0C Model)",0.477,0.924
