// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb 

// ============================================================
// File Name: altpcie_serdes_3cgx_x2d_gen1_08p.v
// Megafunction Name(s):
// 			alt_c3gxb
//
// Simulation Library Files(s):
// 			altera_mf;cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 345 02/24/2010 SP 2 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=2 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="high" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" preemphasis_ctrl_1stposttap_setting=18 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x2" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=2 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_channel_bonding="x2" tx_channel_width=16 tx_clkout_width=2 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=5 cal_blk_clk coreclkout fixedclk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 9.1SP2 cbx_alt_c3gxb 2010:02:24:21:06:43:SJ cbx_altpll 2010:02:24:21:06:43:SJ cbx_cycloneii 2010:02:24:21:06:43:SJ cbx_mgl 2010:02:24:21:13:40:SJ cbx_stingray 2010:02:24:21:06:43:SJ cbx_stratixii 2010:02:24:21:06:43:SJ cbx_util_mgl 2010:02:24:21:06:43:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 2 cycloneiv_hssi_rx_pma 2 cycloneiv_hssi_tx_pcs 2 cycloneiv_hssi_tx_pma 2 reg 3 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module  altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_02q7
	( 
	cal_blk_clk,
	coreclkout,
	fixedclk,
	gxb_powerdown,
	pipe8b10binvpolarity,
	pipedatavalid,
	pipeelecidle,
	pipephydonestatus,
	pipestatus,
	pll_inclk,
	pll_locked,
	powerdn,
	reconfig_clk,
	reconfig_fromgxb,
	reconfig_togxb,
	rx_analogreset,
	rx_ctrldetect,
	rx_datain,
	rx_dataout,
	rx_digitalreset,
	rx_disperr,
	rx_errdetect,
	rx_freqlocked,
	rx_patterndetect,
	rx_syncstatus,
	tx_ctrlenable,
	tx_datain,
	tx_dataout,
	tx_detectrxloop,
	tx_digitalreset,
	tx_forcedispcompliance,
	tx_forceelecidle) /* synthesis synthesis_clearbox=2 */;
	input   cal_blk_clk;
	output   [0:0]  coreclkout;
	input   fixedclk;
	input   [0:0]  gxb_powerdown;
	input   [1:0]  pipe8b10binvpolarity;
	output   [1:0]  pipedatavalid;
	output   [1:0]  pipeelecidle;
	output   [1:0]  pipephydonestatus;
	output   [5:0]  pipestatus;
	input   pll_inclk;
	output   [0:0]  pll_locked;
	input   [3:0]  powerdn;
	input   reconfig_clk;
	output   [4:0]  reconfig_fromgxb;
	input   [3:0]  reconfig_togxb;
	input   [0:0]  rx_analogreset;
	output   [3:0]  rx_ctrldetect;
	input   [1:0]  rx_datain;
	output   [31:0]  rx_dataout;
	input   [0:0]  rx_digitalreset;
	output   [3:0]  rx_disperr;
	output   [3:0]  rx_errdetect;
	output   [1:0]  rx_freqlocked;
	output   [3:0]  rx_patterndetect;
	output   [3:0]  rx_syncstatus;
	input   [3:0]  tx_ctrlenable;
	input   [31:0]  tx_datain;
	output   [1:0]  tx_dataout;
	input   [1:0]  tx_detectrxloop;
	input   [0:0]  tx_digitalreset;
	input   [1:0]  tx_forcedispcompliance;
	input   [1:0]  tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   cal_blk_clk;
	tri0   fixedclk;
	tri0   [0:0]  gxb_powerdown;
	tri0   [1:0]  pipe8b10binvpolarity;
	tri0   [3:0]  powerdn;
	tri0   reconfig_clk;
	tri0   [0:0]  rx_analogreset;
	tri0   [0:0]  rx_digitalreset;
	tri0   [3:0]  tx_ctrlenable;
	tri0   [31:0]  tx_datain;
	tri0   [1:0]  tx_detectrxloop;
	tri0   [0:0]  tx_digitalreset;
	tri0   [1:0]  tx_forcedispcompliance;
	tri0   [1:0]  tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif


	parameter	starting_channel_number = 0;


	wire  [5:0]   wire_pll0_clk;
	wire  wire_pll0_fref;
	wire  wire_pll0_icdrclk;
	wire  wire_pll0_locked;
	wire  wire_cal_blk0_nonusertocmu;
	wire  wire_cent_unit0_coreclkout;
	wire  wire_cent_unit0_dprioout;
	wire  wire_cent_unit0_quadresetout;
	wire  wire_cent_unit0_refclkout;
	wire  [3:0]   wire_cent_unit0_rxanalogresetout;
	wire  [3:0]   wire_cent_unit0_rxcrupowerdown;
	wire  [3:0]   wire_cent_unit0_rxdigitalresetout;
	wire  [3:0]   wire_cent_unit0_rxibpowerdown;
	wire  wire_cent_unit0_rxphfifox4byteselout;
	wire  wire_cent_unit0_rxphfifox4rdenableout;
	wire  wire_cent_unit0_rxphfifox4wrclkout;
	wire  wire_cent_unit0_rxphfifox4wrenableout;
	wire  [3:0]   wire_cent_unit0_txanalogresetout;
	wire  [3:0]   wire_cent_unit0_txdetectrxpowerdown;
	wire  [3:0]   wire_cent_unit0_txdigitalresetout;
	wire  [3:0]   wire_cent_unit0_txdividerpowerdown;
	wire  [3:0]   wire_cent_unit0_txobpowerdown;
	wire  wire_cent_unit0_txphfifox4byteselout;
	wire  wire_cent_unit0_txphfifox4rdclkout;
	wire  wire_cent_unit0_txphfifox4rdenableout;
	wire  wire_cent_unit0_txphfifox4wrenableout;
	wire  wire_receive_pcs0_cdrctrlearlyeios;
	wire  wire_receive_pcs0_cdrctrllocktorefclkout;
	wire  wire_receive_pcs0_coreclkout;
	wire  [1:0]   wire_receive_pcs0_ctrldetect;
	wire  [19:0]   wire_receive_pcs0_dataout;
	wire  [1:0]   wire_receive_pcs0_disperr;
	wire  [1:0]   wire_receive_pcs0_errdetect;
	wire  [1:0]   wire_receive_pcs0_patterndetect;
	wire  wire_receive_pcs0_phfifordenableout;
	wire  wire_receive_pcs0_phfiforesetout;
	wire  wire_receive_pcs0_phfifowrdisableout;
	wire  wire_receive_pcs0_pipedatavalid;
	wire  wire_receive_pcs0_pipeelecidle;
	wire  wire_receive_pcs0_pipephydonestatus;
	wire  [2:0]   wire_receive_pcs0_pipestatus;
	wire  [19:0]   wire_receive_pcs0_revparallelfdbkdata;
	wire  wire_receive_pcs0_signaldetect;
	wire  [1:0]   wire_receive_pcs0_syncstatus;
	wire  wire_receive_pcs1_cdrctrlearlyeios;
	wire  wire_receive_pcs1_cdrctrllocktorefclkout;
	wire  wire_receive_pcs1_coreclkout;
	wire  [1:0]   wire_receive_pcs1_ctrldetect;
	wire  [19:0]   wire_receive_pcs1_dataout;
	wire  [1:0]   wire_receive_pcs1_disperr;
	wire  [1:0]   wire_receive_pcs1_errdetect;
	wire  [1:0]   wire_receive_pcs1_patterndetect;
	wire  wire_receive_pcs1_phfifordenableout;
	wire  wire_receive_pcs1_phfiforesetout;
	wire  wire_receive_pcs1_phfifowrdisableout;
	wire  wire_receive_pcs1_pipedatavalid;
	wire  wire_receive_pcs1_pipeelecidle;
	wire  wire_receive_pcs1_pipephydonestatus;
	wire  [2:0]   wire_receive_pcs1_pipestatus;
	wire  [19:0]   wire_receive_pcs1_revparallelfdbkdata;
	wire  wire_receive_pcs1_signaldetect;
	wire  [1:0]   wire_receive_pcs1_syncstatus;
	wire  [7:0]   wire_receive_pma0_analogtestbus;
	wire  wire_receive_pma0_clockout;
	wire  wire_receive_pma0_freqlocked;
	wire  wire_receive_pma0_locktorefout;
	wire  [9:0]   wire_receive_pma0_recoverdataout;
	wire  wire_receive_pma0_signaldetect;
	wire  [7:0]   wire_receive_pma1_analogtestbus;
	wire  wire_receive_pma1_clockout;
	wire  wire_receive_pma1_freqlocked;
	wire  wire_receive_pma1_locktorefout;
	wire  [9:0]   wire_receive_pma1_recoverdataout;
	wire  wire_receive_pma1_signaldetect;
	wire  wire_transmit_pcs0_coreclkout;
	wire  [9:0]   wire_transmit_pcs0_dataout;
	wire  wire_transmit_pcs0_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs0_grayelecidleinferselout;
	wire  wire_transmit_pcs0_phfiforddisableout;
	wire  wire_transmit_pcs0_phfiforesetout;
	wire  wire_transmit_pcs0_phfifowrenableout;
	wire  wire_transmit_pcs0_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs0_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs0_pipepowerstateout;
	wire  wire_transmit_pcs0_txdetectrx;
	wire  wire_transmit_pcs1_coreclkout;
	wire  [9:0]   wire_transmit_pcs1_dataout;
	wire  wire_transmit_pcs1_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs1_grayelecidleinferselout;
	wire  wire_transmit_pcs1_phfiforddisableout;
	wire  wire_transmit_pcs1_phfiforesetout;
	wire  wire_transmit_pcs1_phfifowrenableout;
	wire  wire_transmit_pcs1_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs1_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs1_pipepowerstateout;
	wire  wire_transmit_pcs1_txdetectrx;
	wire  wire_transmit_pma0_clockout;
	wire  wire_transmit_pma0_dataout;
	wire  wire_transmit_pma0_rxdetectvalidout;
	wire  wire_transmit_pma0_rxfoundout;
	wire  wire_transmit_pma1_clockout;
	wire  wire_transmit_pma1_dataout;
	wire  wire_transmit_pma1_rxdetectvalidout;
	wire  wire_transmit_pma1_rxfoundout;
	reg	[0:0]	fixedclk_div;
	reg	[1:0]	reconfig_togxb_busy_reg;
	wire cal_blk_powerdown;
	wire  [1:0]  cent_unit_quadresetout;
	wire  [1:0]  cent_unit_rxcrupowerdn;
	wire  [1:0]  cent_unit_rxibpowerdn;
	wire  [1:0]  cent_unit_txdetectrxpowerdn;
	wire  [1:0]  cent_unit_txdividerpowerdown;
	wire  [1:0]  cent_unit_txobpowerdn;
	wire  [0:0]  coreclkout_wire;
	wire  [0:0]  fixedclk_div_in;
	wire  [0:0]  fixedclk_enable;
	wire [3:0]  fixedclk_fast;
	wire  [0:0]  fixedclk_sel;
	wire  [1:0]  fixedclk_to_cmu;
	wire  [5:0]  grayelecidleinfersel_from_tx;
	wire  [1:0]  int_pipeenrevparallellpbkfromtx;
	wire  [1:0]  int_rx_coreclkout;
	wire  [1:0]  int_rx_phfifordenableout;
	wire  [1:0]  int_rx_phfiforesetout;
	wire  [1:0]  int_rx_phfifowrdisableout;
	wire  [1:0]  int_rx_phfifoxnbytesel;
	wire  [1:0]  int_rx_phfifoxnrdenable;
	wire  [1:0]  int_rx_phfifoxnwrclk;
	wire  [1:0]  int_rx_phfifoxnwrenable;
	wire  [0:0]  int_rxcoreclk;
	wire  [0:0]  int_rxphfifordenable;
	wire  [0:0]  int_rxphfiforeset;
	wire  [0:0]  int_rxphfifox4byteselout;
	wire  [0:0]  int_rxphfifox4rdenableout;
	wire  [0:0]  int_rxphfifox4wrclkout;
	wire  [0:0]  int_rxphfifox4wrenableout;
	wire  [1:0]  int_tx_coreclkout;
	wire  [1:0]  int_tx_phfiforddisableout;
	wire  [1:0]  int_tx_phfiforesetout;
	wire  [1:0]  int_tx_phfifowrenableout;
	wire  [1:0]  int_tx_phfifoxnbytesel;
	wire  [1:0]  int_tx_phfifoxnrdclk;
	wire  [1:0]  int_tx_phfifoxnrdenable;
	wire  [1:0]  int_tx_phfifoxnwrenable;
	wire  [0:0]  int_txcoreclk;
	wire  [0:0]  int_txphfiforddisable;
	wire  [0:0]  int_txphfiforeset;
	wire  [0:0]  int_txphfifowrenable;
	wire  [0:0]  int_txphfifox4byteselout;
	wire  [0:0]  int_txphfifox4rdclkout;
	wire  [0:0]  int_txphfifox4rdenableout;
	wire  [0:0]  int_txphfifox4wrenableout;
	wire  [0:0]  nonusertocmu_out;
	wire  [1:0]  pipedatavalid_out;
	wire  [1:0]  pipeelecidle_out;
	wire [0:0]  pll_powerdown;
	wire  [0:0]  reconfig_togxb_busy;
	wire  [0:0]  reconfig_togxb_disable;
	wire  [0:0]  reconfig_togxb_in;
	wire  [0:0]  reconfig_togxb_load;
	wire  [0:0]  refclk_pma;
	wire  [1:0]  rx_analogreset_in;
	wire  [1:0]  rx_analogreset_out;
	wire  [1:0]  rx_coreclk_in;
	wire  [1:0]  rx_deserclock_in;
	wire  [1:0]  rx_digitalreset_in;
	wire  [1:0]  rx_digitalreset_out;
	wire [5:0]  rx_elecidleinfersel;
	wire [1:0]  rx_enapatternalign;
	wire [1:0]  rx_locktodata;
	wire  [1:0]  rx_locktorefclk_wire;
	wire  [31:0]  rx_out_wire;
	wire  [3:0]  rx_pcs_rxfound_wire;
	wire [1:0]  rx_phfifordenable;
	wire [1:0]  rx_phfiforeset;
	wire [1:0]  rx_phfifowrdisable;
	wire  [1:0]  rx_pll_pfdrefclkout_wire;
	wire  [4:0]  rx_pma_analogtestbus;
	wire  [1:0]  rx_pma_clockout;
	wire  [19:0]  rx_pma_recoverdataout_wire;
	wire [1:0]  rx_powerdown;
	wire  [1:0]  rx_powerdown_in;
	wire [1:0]  rx_prbscidenable;
	wire  [39:0]  rx_revparallelfdbkdata;
	wire [1:0]  rx_rmfiforeset;
	wire  [1:0]  rx_signaldetect_wire;
	wire  [0:0]  rxphfifowrdisable;
	wire  [1:0]  tx_analogreset_out;
	wire  [1:0]  tx_clkout_int_wire;
	wire  [1:0]  tx_coreclk_in;
	wire  [31:0]  tx_datain_wire;
	wire  [19:0]  tx_dataout_pcs_to_pma;
	wire  [1:0]  tx_digitalreset_in;
	wire  [1:0]  tx_digitalreset_out;
	wire  [3:0]  tx_forcedisp_wire;
	wire [1:0]  tx_invpolarity;
	wire  [1:0]  tx_localrefclk;
	wire  [1:0]  tx_pcs_forceelecidleout;
	wire [1:0]  tx_phfiforeset;
	wire  [3:0]  tx_pipepowerdownout;
	wire  [7:0]  tx_pipepowerstateout;
	wire  [1:0]  tx_pma_fastrefclk0in;
	wire  [1:0]  tx_pma_refclk0in;
	wire  [1:0]  tx_pma_refclk0inpulse;
	wire [1:0]  tx_revparallellpbken;
	wire  [1:0]  tx_rxdetectvalidout;
	wire  [1:0]  tx_rxfoundout;
	wire  [1:0]  txdataout;
	wire  [1:0]  txdetectrxout;

	altpll   pll0
	( 
	.activeclock(),
	.areset(pll_powerdown[0]),
	.clk(wire_pll0_clk),
	.clkbad(),
	.clkloss(),
	.enable0(),
	.enable1(),
	.extclk(),
	.fbout(),
	.fref(wire_pll0_fref),
	.icdrclk(wire_pll0_icdrclk),
	.inclk({{1{1'b0}}, pll_inclk}),
	.locked(wire_pll0_locked),
	.phasedone(),
	.scandataout(),
	.scandone(),
	.sclkout0(),
	.sclkout1(),
	.vcooverrange(),
	.vcounderrange()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.clkena({6{1'b1}}),
	.clkswitch(1'b0),
	.configupdate(1'b0),
	.extclkena({4{1'b1}}),
	.fbin(1'b1),
	.pfdena(1'b1),
	.phasecounterselect({4{1'b1}}),
	.phasestep(1'b1),
	.phaseupdown(1'b1),
	.pllena(1'b1),
	.scanaclr(1'b0),
	.scanclk(1'b0),
	.scanclkena(1'b1),
	.scandata(1'b0),
	.scanread(1'b0),
	.scanwrite(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		pll0.bandwidth_type = "HIGH",
		pll0.clk0_divide_by = 2,
		pll0.clk0_multiply_by = 25,
		pll0.clk1_divide_by = 10,
		pll0.clk1_multiply_by = 25,
		pll0.clk2_divide_by = 10,
		pll0.clk2_duty_cycle = 20,
		pll0.clk2_multiply_by = 25,
		pll0.dpa_divide_by = 2,
		pll0.dpa_multiply_by = 25,
		pll0.inclk0_input_frequency = 10000,
		pll0.operation_mode = "no_compensation",
		pll0.intended_device_family = "Cyclone IV GX",
		pll0.lpm_type = "altpll";
	cycloneiv_hssi_calibration_block   cal_blk0
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.nonusertocmu(wire_cal_blk0_nonusertocmu),
	.powerdn(cal_blk_powerdown)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.testctrl(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	cycloneiv_hssi_cmu   cent_unit0
	( 
	.alignstatus(),
	.coreclkout(wire_cent_unit0_coreclkout),
	.digitaltestout(),
	.dpclk(reconfig_clk),
	.dpriodisable(reconfig_togxb_disable),
	.dpriodisableout(),
	.dprioin(reconfig_togxb_in),
	.dprioload(reconfig_togxb_load),
	.dpriooe(),
	.dprioout(wire_cent_unit0_dprioout),
	.enabledeskew(),
	.fiforesetrd(),
	.fixedclk({{2{1'b0}}, fixedclk_to_cmu[1:0]}),
	.nonuserfromcal(nonusertocmu_out[0]),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_cent_unit0_quadresetout),
	.refclkout(wire_cent_unit0_refclkout),
	.rxanalogreset({{2{1'b0}}, rx_analogreset_in[1:0]}),
	.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
	.rxcoreclk(int_rxcoreclk[0]),
	.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
	.rxctrlout(),
	.rxdataout(),
	.rxdigitalreset({{2{1'b0}}, rx_digitalreset_in[1:0]}),
	.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
	.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
	.rxphfifordenable(int_rxphfifordenable[0]),
	.rxphfiforeset(int_rxphfiforeset[0]),
	.rxphfifowrdisable(rxphfifowrdisable[0]),
	.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
	.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
	.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
	.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
	.rxpowerdown({{2{1'b0}}, rx_powerdown_in[1:0]}),
	.testout(),
	.txanalogresetout(wire_cent_unit0_txanalogresetout),
	.txclk(tx_localrefclk[0]),
	.txcoreclk(int_txcoreclk[0]),
	.txctrlout(),
	.txdataout(),
	.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
	.txdigitalreset({{2{1'b0}}, tx_digitalreset_in[1:0]}),
	.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
	.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
	.txobpowerdown(wire_cent_unit0_txobpowerdown),
	.txphfiforddisable(int_txphfiforddisable[0]),
	.txphfiforeset(int_txphfiforeset[0]),
	.txphfifowrenable(int_txphfifowrenable[0]),
	.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
	.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
	.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
	.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adet({4{1'b0}}),
	.pmacramtest(1'b0),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b1),
	.recovclk(1'b0),
	.refclkdig(1'b0),
	.rxctrl({4{1'b0}}),
	.rxdatain({32{1'b0}}),
	.rxdatavalid({4{1'b0}}),
	.rxrunningdisp({4{1'b0}}),
	.scanclk(1'b0),
	.scanmode(1'b0),
	.scanshift(1'b0),
	.syncstatus({4{1'b0}}),
	.testin({2000{1'b0}}),
	.txctrl({4{1'b0}}),
	.txdatain({32{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
		cent_unit0.auto_spd_phystatus_notify_count = 14,
		cent_unit0.in_xaui_mode = "false",
		cent_unit0.rx0_channel_bonding = "x2",
		cent_unit0.rx0_clk1_mux_select = "recovered clock",
		cent_unit0.rx0_clk2_mux_select = "digital reference clock",
		cent_unit0.rx0_ph_fifo_reg_mode = "false",
		cent_unit0.rx0_rd_clk_mux_select = "core clock",
		cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
		cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
		cent_unit0.rx0_use_double_data_mode = "true",
		cent_unit0.tx0_channel_bonding = "x2",
		cent_unit0.tx0_rd_clk_mux_select = "central",
		cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
		cent_unit0.tx0_use_double_data_mode = "true",
		cent_unit0.tx0_wr_clk_mux_select = "core_clk",
		cent_unit0.use_coreclk_out_post_divider = "true",
		cent_unit0.use_deskew_fifo = "false",
		cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
	cycloneiv_hssi_rx_pcs   receive_pcs0
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatussyncout(),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
	.clkout(),
	.coreclk(rx_coreclk_in[0]),
	.coreclkout(wire_receive_pcs0_coreclkout),
	.ctrldetect(wire_receive_pcs0_ctrldetect),
	.datain(rx_pma_recoverdataout_wire[9:0]),
	.dataout(wire_receive_pcs0_dataout),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[0]),
	.disperr(wire_receive_pcs0_disperr),
	.elecidleinfersel({3{1'b0}}),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[0]),
	.errdetect(wire_receive_pcs0_errdetect),
	.fifordout(),
	.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
	.hipdataout(),
	.hipdatavalid(),
	.hipelecidle(),
	.hipphydonestatus(),
	.hipstatus(),
	.invpol(1'b0),
	.k1detect(),
	.k2detect(),
	.localrefclk(tx_localrefclk[0]),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(wire_receive_pcs0_patterndetect),
	.phfifooverflow(),
	.phfifordenable(rx_phfifordenable[0]),
	.phfifordenableout(wire_receive_pcs0_phfifordenableout),
	.phfiforeset(rx_phfiforeset[0]),
	.phfiforesetout(wire_receive_pcs0_phfiforesetout),
	.phfifounderflow(),
	.phfifowrdisable(rx_phfifowrdisable[0]),
	.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
	.phfifox4bytesel(int_rx_phfifoxnbytesel[0]),
	.phfifox4rdenable(int_rx_phfifoxnrdenable[0]),
	.phfifox4wrclk(int_rx_phfifoxnwrclk[0]),
	.phfifox4wrenable(int_rx_phfifoxnwrenable[0]),
	.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
	.pipebufferstat(),
	.pipedatavalid(wire_receive_pcs0_pipedatavalid),
	.pipeelecidle(wire_receive_pcs0_pipeelecidle),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
	.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
	.pipepowerdown(tx_pipepowerdownout[1:0]),
	.pipepowerstate(tx_pipepowerstateout[3:0]),
	.pipestatus(wire_receive_pcs0_pipestatus),
	.powerdn(powerdn[1:0]),
	.prbscidenable(rx_prbscidenable[0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[0]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
	.rlv(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[0]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[0]),
	.rxfound(rx_pcs_rxfound_wire[1:0]),
	.signaldetect(wire_receive_pcs0_signaldetect),
	.signaldetected(rx_signaldetect_wire[0]),
	.syncstatus(wire_receive_pcs0_syncstatus),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.enabledeskew(1'b0),
	.fifordin(1'b0),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hippowerdown({2{1'b0}}),
	.masterclk(1'b0),
	.pmatestbusin({8{1'b0}}),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs0.align_pattern = "0101111100",
		receive_pcs0.align_pattern_length = 10,
		receive_pcs0.allow_align_polarity_inversion = "false",
		receive_pcs0.allow_pipe_polarity_inversion = "true",
		receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs0.auto_spd_phystatus_notify_count = 14,
		receive_pcs0.bit_slip_enable = "false",
		receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs0.byte_order_mode = "none",
		receive_pcs0.byte_order_pad_pattern = "0",
		receive_pcs0.byte_order_pattern = "0",
		receive_pcs0.byte_order_pld_ctrl_enable = "false",
		receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs0.cdrctrl_cid_mode_enable = "true",
		receive_pcs0.cdrctrl_enable = "true",
		receive_pcs0.cdrctrl_mask_cycle = 800,
		receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
		receive_pcs0.cdrctrl_rxvalid_mask = "true",
		receive_pcs0.channel_bonding = "x2",
		receive_pcs0.channel_number = ((starting_channel_number + 0) % 2),
		receive_pcs0.channel_width = 16,
		receive_pcs0.clk1_mux_select = "recovered clock",
		receive_pcs0.clk2_mux_select = "digital reference clock",
		receive_pcs0.datapath_low_latency_mode = "false",
		receive_pcs0.datapath_protocol = "pipe",
		receive_pcs0.dec_8b_10b_compatibility_mode = "true",
		receive_pcs0.dec_8b_10b_mode = "normal",
		receive_pcs0.deskew_pattern = "0",
		receive_pcs0.disable_auto_idle_insertion = "false",
		receive_pcs0.disable_running_disp_in_word_align = "false",
		receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs0.elec_idle_infer_enable = "false",
		receive_pcs0.elec_idle_num_com_detect = 3,
		receive_pcs0.enable_bit_reversal = "false",
		receive_pcs0.enable_self_test_mode = "false",
		receive_pcs0.force_signal_detect_dig = "true",
		receive_pcs0.hip_enable = "false",
		receive_pcs0.infiniband_invalid_code = 0,
		receive_pcs0.insert_pad_on_underflow = "false",
		receive_pcs0.num_align_code_groups_in_ordered_set = 0,
		receive_pcs0.num_align_cons_good_data = 16,
		receive_pcs0.num_align_cons_pat = 4,
		receive_pcs0.num_align_loss_sync_error = 17,
		receive_pcs0.ph_fifo_low_latency_enable = "true",
		receive_pcs0.ph_fifo_reg_mode = "false",
		receive_pcs0.protocol_hint = "pcie",
		receive_pcs0.rate_match_back_to_back = "false",
		receive_pcs0.rate_match_delete_threshold = 13,
		receive_pcs0.rate_match_empty_threshold = 5,
		receive_pcs0.rate_match_fifo_mode = "true",
		receive_pcs0.rate_match_full_threshold = 20,
		receive_pcs0.rate_match_insert_threshold = 11,
		receive_pcs0.rate_match_ordered_set_based = "false",
		receive_pcs0.rate_match_pattern1 = "11010000111010000011",
		receive_pcs0.rate_match_pattern2 = "00101111000101111100",
		receive_pcs0.rate_match_pattern_size = 20,
		receive_pcs0.rate_match_pipe_enable = "true",
		receive_pcs0.rate_match_reset_enable = "false",
		receive_pcs0.rate_match_skip_set_based = "true",
		receive_pcs0.rate_match_start_threshold = 7,
		receive_pcs0.rd_clk_mux_select = "core clock",
		receive_pcs0.recovered_clk_mux_select = "recovered clock",
		receive_pcs0.run_length = 40,
		receive_pcs0.run_length_enable = "true",
		receive_pcs0.rx_detect_bypass = "false",
		receive_pcs0.rx_phfifo_wait_cnt = 32,
		receive_pcs0.rxstatus_error_report_mode = 1,
		receive_pcs0.self_test_mode = "incremental",
		receive_pcs0.use_alignment_state_machine = "true",
		receive_pcs0.use_deskew_fifo = "false",
		receive_pcs0.use_double_data_mode = "true",
		receive_pcs0.use_parallel_loopback = "false",
		receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
	cycloneiv_hssi_rx_pcs   receive_pcs1
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatussyncout(),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
	.clkout(),
	.coreclk(rx_coreclk_in[1]),
	.coreclkout(wire_receive_pcs1_coreclkout),
	.ctrldetect(wire_receive_pcs1_ctrldetect),
	.datain(rx_pma_recoverdataout_wire[19:10]),
	.dataout(wire_receive_pcs1_dataout),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[1]),
	.disperr(wire_receive_pcs1_disperr),
	.elecidleinfersel({3{1'b0}}),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[1]),
	.errdetect(wire_receive_pcs1_errdetect),
	.fifordout(),
	.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
	.hipdataout(),
	.hipdatavalid(),
	.hipelecidle(),
	.hipphydonestatus(),
	.hipstatus(),
	.invpol(1'b0),
	.k1detect(),
	.k2detect(),
	.localrefclk(tx_localrefclk[1]),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(wire_receive_pcs1_patterndetect),
	.phfifooverflow(),
	.phfifordenable(rx_phfifordenable[1]),
	.phfifordenableout(wire_receive_pcs1_phfifordenableout),
	.phfiforeset(rx_phfiforeset[1]),
	.phfiforesetout(wire_receive_pcs1_phfiforesetout),
	.phfifounderflow(),
	.phfifowrdisable(rx_phfifowrdisable[1]),
	.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
	.phfifox4bytesel(int_rx_phfifoxnbytesel[1]),
	.phfifox4rdenable(int_rx_phfifoxnrdenable[1]),
	.phfifox4wrclk(int_rx_phfifoxnwrclk[1]),
	.phfifox4wrenable(int_rx_phfifoxnwrenable[1]),
	.pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
	.pipebufferstat(),
	.pipedatavalid(wire_receive_pcs1_pipedatavalid),
	.pipeelecidle(wire_receive_pcs1_pipeelecidle),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
	.pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
	.pipepowerdown(tx_pipepowerdownout[3:2]),
	.pipepowerstate(tx_pipepowerstateout[7:4]),
	.pipestatus(wire_receive_pcs1_pipestatus),
	.powerdn(powerdn[3:2]),
	.prbscidenable(rx_prbscidenable[1]),
	.quadreset(cent_unit_quadresetout[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[1]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
	.rlv(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[1]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[1]),
	.rxfound(rx_pcs_rxfound_wire[3:2]),
	.signaldetect(wire_receive_pcs1_signaldetect),
	.signaldetected(rx_signaldetect_wire[1]),
	.syncstatus(wire_receive_pcs1_syncstatus),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.enabledeskew(1'b0),
	.fifordin(1'b0),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hippowerdown({2{1'b0}}),
	.masterclk(1'b0),
	.pmatestbusin({8{1'b0}}),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs1.align_pattern = "0101111100",
		receive_pcs1.align_pattern_length = 10,
		receive_pcs1.allow_align_polarity_inversion = "false",
		receive_pcs1.allow_pipe_polarity_inversion = "true",
		receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs1.auto_spd_phystatus_notify_count = 14,
		receive_pcs1.bit_slip_enable = "false",
		receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs1.byte_order_mode = "none",
		receive_pcs1.byte_order_pad_pattern = "0",
		receive_pcs1.byte_order_pattern = "0",
		receive_pcs1.byte_order_pld_ctrl_enable = "false",
		receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs1.cdrctrl_cid_mode_enable = "true",
		receive_pcs1.cdrctrl_enable = "true",
		receive_pcs1.cdrctrl_mask_cycle = 800,
		receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
		receive_pcs1.cdrctrl_rxvalid_mask = "true",
		receive_pcs1.channel_bonding = "x2",
		receive_pcs1.channel_number = ((starting_channel_number + 1) % 2),
		receive_pcs1.channel_width = 16,
		receive_pcs1.clk1_mux_select = "recovered clock",
		receive_pcs1.clk2_mux_select = "digital reference clock",
		receive_pcs1.datapath_low_latency_mode = "false",
		receive_pcs1.datapath_protocol = "pipe",
		receive_pcs1.dec_8b_10b_compatibility_mode = "true",
		receive_pcs1.dec_8b_10b_mode = "normal",
		receive_pcs1.deskew_pattern = "0",
		receive_pcs1.disable_auto_idle_insertion = "false",
		receive_pcs1.disable_running_disp_in_word_align = "false",
		receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs1.elec_idle_infer_enable = "false",
		receive_pcs1.elec_idle_num_com_detect = 3,
		receive_pcs1.enable_bit_reversal = "false",
		receive_pcs1.enable_self_test_mode = "false",
		receive_pcs1.force_signal_detect_dig = "true",
		receive_pcs1.hip_enable = "false",
		receive_pcs1.infiniband_invalid_code = 0,
		receive_pcs1.insert_pad_on_underflow = "false",
		receive_pcs1.num_align_code_groups_in_ordered_set = 0,
		receive_pcs1.num_align_cons_good_data = 16,
		receive_pcs1.num_align_cons_pat = 4,
		receive_pcs1.num_align_loss_sync_error = 17,
		receive_pcs1.ph_fifo_low_latency_enable = "true",
		receive_pcs1.ph_fifo_reg_mode = "false",
		receive_pcs1.protocol_hint = "pcie",
		receive_pcs1.rate_match_back_to_back = "false",
		receive_pcs1.rate_match_delete_threshold = 13,
		receive_pcs1.rate_match_empty_threshold = 5,
		receive_pcs1.rate_match_fifo_mode = "true",
		receive_pcs1.rate_match_full_threshold = 20,
		receive_pcs1.rate_match_insert_threshold = 11,
		receive_pcs1.rate_match_ordered_set_based = "false",
		receive_pcs1.rate_match_pattern1 = "11010000111010000011",
		receive_pcs1.rate_match_pattern2 = "00101111000101111100",
		receive_pcs1.rate_match_pattern_size = 20,
		receive_pcs1.rate_match_pipe_enable = "true",
		receive_pcs1.rate_match_reset_enable = "false",
		receive_pcs1.rate_match_skip_set_based = "true",
		receive_pcs1.rate_match_start_threshold = 7,
		receive_pcs1.rd_clk_mux_select = "core clock",
		receive_pcs1.recovered_clk_mux_select = "recovered clock",
		receive_pcs1.run_length = 40,
		receive_pcs1.run_length_enable = "true",
		receive_pcs1.rx_detect_bypass = "false",
		receive_pcs1.rx_phfifo_wait_cnt = 32,
		receive_pcs1.rxstatus_error_report_mode = 1,
		receive_pcs1.self_test_mode = "incremental",
		receive_pcs1.use_alignment_state_machine = "true",
		receive_pcs1.use_deskew_fifo = "false",
		receive_pcs1.use_double_data_mode = "true",
		receive_pcs1.use_parallel_loopback = "false",
		receive_pcs1.lpm_type = "cycloneiv_hssi_rx_pcs";
	cycloneiv_hssi_rx_pma   receive_pma0
	( 
	.analogtestbus(wire_receive_pma0_analogtestbus),
	.clockout(wire_receive_pma0_clockout),
	.crupowerdn(cent_unit_rxcrupowerdn[0]),
	.datain(rx_datain[0]),
	.datastrobeout(),
	.deserclock(rx_deserclock_in[0]),
	.diagnosticlpbkout(),
	.freqlocked(wire_receive_pma0_freqlocked),
	.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
	.locktoref(rx_locktorefclk_wire[0]),
	.locktorefout(wire_receive_pma0_locktorefout),
	.powerdn(cent_unit_rxibpowerdn[0]),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
	.recoverdataout(wire_receive_pma0_recoverdataout),
	.reverselpbkout(),
	.rxpmareset(rx_analogreset_out[0]),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma0_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.dpashift(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma0.allow_serial_loopback = "false",
		receive_pma0.channel_number = ((starting_channel_number + 0) % 2),
		receive_pma0.common_mode = "0.82V",
		receive_pma0.deserialization_factor = 10,
		receive_pma0.effective_data_rate = "2500 Mbps",
		receive_pma0.enable_ltd = "false",
		receive_pma0.enable_ltr = "false",
		receive_pma0.eq_dc_gain = 3,
		receive_pma0.eq_setting = 1,
		receive_pma0.force_signal_detect = "false",
		receive_pma0.offset_cancellation = 1,
		receive_pma0.ppm_gen1_2_xcnt_en = 1,
		receive_pma0.ppm_post_eidle = 0,
		receive_pma0.ppmselect = 8,
		receive_pma0.protocol_hint = "pcie",
		receive_pma0.signal_detect_hysteresis = 4,
		receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
		receive_pma0.signal_detect_loss_threshold = 3,
		receive_pma0.termination = "OCT 100 Ohms",
		receive_pma0.use_external_termination = "false",
		receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
	cycloneiv_hssi_rx_pma   receive_pma1
	( 
	.analogtestbus(wire_receive_pma1_analogtestbus),
	.clockout(wire_receive_pma1_clockout),
	.crupowerdn(cent_unit_rxcrupowerdn[1]),
	.datain(rx_datain[1]),
	.datastrobeout(),
	.deserclock(rx_deserclock_in[1]),
	.diagnosticlpbkout(),
	.freqlocked(wire_receive_pma1_freqlocked),
	.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[1])),
	.locktoref(rx_locktorefclk_wire[1]),
	.locktorefout(wire_receive_pma1_locktorefout),
	.powerdn(cent_unit_rxibpowerdn[1]),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
	.recoverdataout(wire_receive_pma1_recoverdataout),
	.reverselpbkout(),
	.rxpmareset(rx_analogreset_out[1]),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma1_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.dpashift(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma1.allow_serial_loopback = "false",
		receive_pma1.channel_number = ((starting_channel_number + 1) % 2),
		receive_pma1.common_mode = "0.82V",
		receive_pma1.deserialization_factor = 10,
		receive_pma1.effective_data_rate = "2500 Mbps",
		receive_pma1.enable_ltd = "false",
		receive_pma1.enable_ltr = "false",
		receive_pma1.eq_dc_gain = 3,
		receive_pma1.eq_setting = 1,
		receive_pma1.force_signal_detect = "false",
		receive_pma1.offset_cancellation = 1,
		receive_pma1.ppm_gen1_2_xcnt_en = 1,
		receive_pma1.ppm_post_eidle = 0,
		receive_pma1.ppmselect = 8,
		receive_pma1.protocol_hint = "pcie",
		receive_pma1.signal_detect_hysteresis = 4,
		receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
		receive_pma1.signal_detect_loss_threshold = 3,
		receive_pma1.termination = "OCT 100 Ohms",
		receive_pma1.use_external_termination = "false",
		receive_pma1.lpm_type = "cycloneiv_hssi_rx_pma";
	cycloneiv_hssi_tx_pcs   transmit_pcs0
	( 
	.clkout(),
	.coreclk(tx_coreclk_in[0]),
	.coreclkout(wire_transmit_pcs0_coreclkout),
	.ctrlenable({tx_ctrlenable[1:0]}),
	.datain({{4{1'b0}}, tx_datain_wire[15:0]}),
	.dataout(wire_transmit_pcs0_dataout),
	.detectrxloop(tx_detectrxloop[0]),
	.digitalreset(tx_digitalreset_out[0]),
	.dispval({2{tx_forceelecidle[0]}}),
	.elecidleinfersel(rx_elecidleinfersel[2:0]),
	.enrevparallellpbk(tx_revparallellpbken[0]),
	.forcedisp({tx_forcedisp_wire[1:0]}),
	.forceelecidle(tx_forceelecidle[0]),
	.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
	.hiptxclkout(),
	.invpol(tx_invpolarity[0]),
	.localrefclk(tx_localrefclk[0]),
	.parallelfdbkout(),
	.phfifooverflow(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
	.phfiforeset(tx_phfiforeset[0]),
	.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
	.phfifox4bytesel(int_tx_phfifoxnbytesel[0]),
	.phfifox4rdclk(int_tx_phfifoxnrdclk[0]),
	.phfifox4rdenable(int_tx_phfifoxnrdenable[0]),
	.phfifox4wrenable(int_tx_phfifoxnwrenable[0]),
	.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
	.powerdn(powerdn[1:0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
	.txdetectrx(wire_transmit_pcs0_txdetectrx),
	.xgmctrlenable(),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.datainfull({22{1'b0}}),
	.hipdatain({10{1'b0}}),
	.hipdetectrxloop(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hipforceelecidle(1'b0),
	.hippowerdn({2{1'b0}}),
	.pipetxswing(1'b0),
	.prbscidenable(1'b0),
	.xgmctrl(1'b0),
	.xgmdatain({8{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs0.allow_polarity_inversion = "false",
		transmit_pcs0.bitslip_enable = "false",
		transmit_pcs0.channel_bonding = "x2",
		transmit_pcs0.channel_number = ((starting_channel_number + 0) % 2),
		transmit_pcs0.channel_width = 16,
		transmit_pcs0.datapath_low_latency_mode = "false",
		transmit_pcs0.datapath_protocol = "pipe",
		transmit_pcs0.disable_ph_low_latency_mode = "false",
		transmit_pcs0.disparity_mode = "new",
		transmit_pcs0.elec_idle_delay = 6,
		transmit_pcs0.enable_bit_reversal = "false",
		transmit_pcs0.enable_idle_selection = "false",
		transmit_pcs0.enable_reverse_parallel_loopback = "true",
		transmit_pcs0.enable_self_test_mode = "false",
		transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs0.enc_8b_10b_mode = "normal",
		transmit_pcs0.hip_enable = "false",
		transmit_pcs0.ph_fifo_reg_mode = "false",
		transmit_pcs0.prbs_cid_pattern = "false",
		transmit_pcs0.protocol_hint = "pcie",
		transmit_pcs0.refclk_select = "central",
		transmit_pcs0.self_test_mode = "incremental",
		transmit_pcs0.use_double_data_mode = "true",
		transmit_pcs0.wr_clk_mux_select = "core_clk",
		transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
	cycloneiv_hssi_tx_pcs   transmit_pcs1
	( 
	.clkout(),
	.coreclk(tx_coreclk_in[1]),
	.coreclkout(wire_transmit_pcs1_coreclkout),
	.ctrlenable({tx_ctrlenable[3:2]}),
	.datain({{4{1'b0}}, tx_datain_wire[31:16]}),
	.dataout(wire_transmit_pcs1_dataout),
	.detectrxloop(tx_detectrxloop[1]),
	.digitalreset(tx_digitalreset_out[1]),
	.dispval({2{tx_forceelecidle[1]}}),
	.elecidleinfersel(rx_elecidleinfersel[5:3]),
	.enrevparallellpbk(tx_revparallellpbken[1]),
	.forcedisp({tx_forcedisp_wire[3:2]}),
	.forceelecidle(tx_forceelecidle[1]),
	.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
	.hiptxclkout(),
	.invpol(tx_invpolarity[1]),
	.localrefclk(tx_localrefclk[1]),
	.parallelfdbkout(),
	.phfifooverflow(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
	.phfiforeset(tx_phfiforeset[1]),
	.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
	.phfifox4bytesel(int_tx_phfifoxnbytesel[1]),
	.phfifox4rdclk(int_tx_phfifoxnrdclk[1]),
	.phfifox4rdenable(int_tx_phfifoxnrdenable[1]),
	.phfifox4wrenable(int_tx_phfifoxnwrenable[1]),
	.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
	.powerdn(powerdn[3:2]),
	.quadreset(cent_unit_quadresetout[0]),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
	.txdetectrx(wire_transmit_pcs1_txdetectrx),
	.xgmctrlenable(),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.datainfull({22{1'b0}}),
	.hipdatain({10{1'b0}}),
	.hipdetectrxloop(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hipforceelecidle(1'b0),
	.hippowerdn({2{1'b0}}),
	.pipetxswing(1'b0),
	.prbscidenable(1'b0),
	.xgmctrl(1'b0),
	.xgmdatain({8{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs1.allow_polarity_inversion = "false",
		transmit_pcs1.bitslip_enable = "false",
		transmit_pcs1.channel_bonding = "x2",
		transmit_pcs1.channel_number = ((starting_channel_number + 1) % 2),
		transmit_pcs1.channel_width = 16,
		transmit_pcs1.datapath_low_latency_mode = "false",
		transmit_pcs1.datapath_protocol = "pipe",
		transmit_pcs1.disable_ph_low_latency_mode = "false",
		transmit_pcs1.disparity_mode = "new",
		transmit_pcs1.elec_idle_delay = 6,
		transmit_pcs1.enable_bit_reversal = "false",
		transmit_pcs1.enable_idle_selection = "false",
		transmit_pcs1.enable_reverse_parallel_loopback = "true",
		transmit_pcs1.enable_self_test_mode = "false",
		transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs1.enc_8b_10b_mode = "normal",
		transmit_pcs1.hip_enable = "false",
		transmit_pcs1.ph_fifo_reg_mode = "false",
		transmit_pcs1.prbs_cid_pattern = "false",
		transmit_pcs1.protocol_hint = "pcie",
		transmit_pcs1.refclk_select = "central",
		transmit_pcs1.self_test_mode = "incremental",
		transmit_pcs1.use_double_data_mode = "true",
		transmit_pcs1.wr_clk_mux_select = "core_clk",
		transmit_pcs1.lpm_type = "cycloneiv_hssi_tx_pcs";
	cycloneiv_hssi_tx_pma   transmit_pma0
	( 
	.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
	.clockout(wire_transmit_pma0_clockout),
	.datain({tx_dataout_pcs_to_pma[9:0]}),
	.dataout(wire_transmit_pma0_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
	.fastrefclk0in(tx_pma_fastrefclk0in[0]),
	.forceelecidle(tx_pcs_forceelecidleout[0]),
	.powerdn(cent_unit_txobpowerdn[0]),
	.refclk0in(tx_pma_refclk0in[0]),
	.refclk0inpulse(tx_pma_refclk0inpulse[0]),
	.reverselpbkin(1'b0),
	.rxdetecten(txdetectrxout[0]),
	.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma0_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[0])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.diagnosticlpbkin(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma0.channel_number = ((starting_channel_number + 0) % 2),
		transmit_pma0.common_mode = "0.65V",
		transmit_pma0.effective_data_rate = "2500 Mbps",
		transmit_pma0.enable_reverse_serial_loopback = "false",
		transmit_pma0.preemp_tap_1 = 18,
		transmit_pma0.protocol_hint = "pcie",
		transmit_pma0.rx_detect = 0,
		transmit_pma0.serialization_factor = 10,
		transmit_pma0.slew_rate = "low",
		transmit_pma0.termination = "OCT 100 Ohms",
		transmit_pma0.use_external_termination = "false",
		transmit_pma0.use_rx_detect = "true",
		transmit_pma0.vod_selection = 5,
		transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
	cycloneiv_hssi_tx_pma   transmit_pma1
	( 
	.cgbpowerdn(cent_unit_txdividerpowerdown[1]),
	.clockout(wire_transmit_pma1_clockout),
	.datain({tx_dataout_pcs_to_pma[19:10]}),
	.dataout(wire_transmit_pma1_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
	.fastrefclk0in(tx_pma_fastrefclk0in[1]),
	.forceelecidle(tx_pcs_forceelecidleout[1]),
	.powerdn(cent_unit_txobpowerdn[1]),
	.refclk0in(tx_pma_refclk0in[1]),
	.refclk0inpulse(tx_pma_refclk0inpulse[1]),
	.reverselpbkin(1'b0),
	.rxdetecten(txdetectrxout[1]),
	.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma1_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[1])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.diagnosticlpbkin(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma1.channel_number = ((starting_channel_number + 1) % 2),
		transmit_pma1.common_mode = "0.65V",
		transmit_pma1.effective_data_rate = "2500 Mbps",
		transmit_pma1.enable_reverse_serial_loopback = "false",
		transmit_pma1.preemp_tap_1 = 18,
		transmit_pma1.protocol_hint = "pcie",
		transmit_pma1.rx_detect = 0,
		transmit_pma1.serialization_factor = 10,
		transmit_pma1.slew_rate = "low",
		transmit_pma1.termination = "OCT 100 Ohms",
		transmit_pma1.use_external_termination = "false",
		transmit_pma1.use_rx_detect = "true",
		transmit_pma1.vod_selection = 5,
		transmit_pma1.lpm_type = "cycloneiv_hssi_tx_pma";
	// synopsys translate_off
	initial
		fixedclk_div = 0;
	// synopsys translate_on
	always @ ( posedge fixedclk)
		  fixedclk_div <= (~ fixedclk_div_in);
	// synopsys translate_off
	initial
		reconfig_togxb_busy_reg = 0;
	// synopsys translate_on
	always @ ( negedge fixedclk)
		  reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
	assign
		cal_blk_powerdown = 1'b0,
		cent_unit_quadresetout = {1'b0, wire_cent_unit0_quadresetout},
		cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[1:0]},
		cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[1:0]},
		cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[1:0]},
		cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[1:0]},
		cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[1:0]},
		coreclkout = {coreclkout_wire[0]},
		coreclkout_wire = {wire_cent_unit0_coreclkout},
		fixedclk_div_in = fixedclk_div,
		fixedclk_enable = reconfig_togxb_busy_reg[0],
		fixedclk_fast = {4{1'b1}},
		fixedclk_sel = reconfig_togxb_busy_reg[1],
		fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
		grayelecidleinfersel_from_tx = {wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
		int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
		int_rx_coreclkout = {wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
		int_rx_phfifordenableout = {wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
		int_rx_phfiforesetout = {wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
		int_rx_phfifowrdisableout = {wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
		int_rx_phfifoxnbytesel = {2{int_rxphfifox4byteselout[0]}},
		int_rx_phfifoxnrdenable = {2{int_rxphfifox4rdenableout[0]}},
		int_rx_phfifoxnwrclk = {2{int_rxphfifox4wrclkout[0]}},
		int_rx_phfifoxnwrenable = {2{int_rxphfifox4wrenableout[0]}},
		int_rxcoreclk = {int_rx_coreclkout[0]},
		int_rxphfifordenable = {int_rx_phfifordenableout[0]},
		int_rxphfiforeset = {int_rx_phfiforesetout[0]},
		int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
		int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
		int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
		int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
		int_tx_coreclkout = {wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
		int_tx_phfiforddisableout = {wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
		int_tx_phfiforesetout = {wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
		int_tx_phfifowrenableout = {wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
		int_tx_phfifoxnbytesel = {2{int_txphfifox4byteselout[0]}},
		int_tx_phfifoxnrdclk = {2{int_txphfifox4rdclkout[0]}},
		int_tx_phfifoxnrdenable = {2{int_txphfifox4rdenableout[0]}},
		int_tx_phfifoxnwrenable = {2{int_txphfifox4wrenableout[0]}},
		int_txcoreclk = {int_tx_coreclkout[0]},
		int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
		int_txphfiforeset = {int_tx_phfiforesetout[0]},
		int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
		int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
		int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
		int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
		int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
		nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
		pipedatavalid = {pipedatavalid_out[1:0]},
		pipedatavalid_out = {wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
		pipeelecidle = {pipeelecidle_out[1:0]},
		pipeelecidle_out = {wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
		pipephydonestatus = {wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
		pipestatus = {wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
		pll_locked = {(wire_pll0_locked & (~ rx_analogreset[0]))},
		pll_powerdown = 1'b0,
		reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
		reconfig_togxb_busy = reconfig_togxb[3],
		reconfig_togxb_disable = reconfig_togxb[1],
		reconfig_togxb_in = reconfig_togxb[0],
		reconfig_togxb_load = reconfig_togxb[2],
		refclk_pma = {wire_cent_unit0_refclkout},
		rx_analogreset_in = {2{((~ reconfig_togxb_busy) & rx_analogreset[0])}},
		rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[1:0]},
		rx_coreclk_in = {2{coreclkout_wire[0]}},
		rx_ctrldetect = {wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
		rx_dataout = {rx_out_wire[31:0]},
		rx_deserclock_in = {2{wire_pll0_icdrclk}},
		rx_digitalreset_in = {2{rx_digitalreset[0]}},
		rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[1:0]},
		rx_disperr = {wire_receive_pcs1_disperr[1:0], wire_receive_pcs0_disperr[1:0]},
		rx_elecidleinfersel = {6{1'b0}},
		rx_enapatternalign = {2{1'b0}},
		rx_errdetect = {wire_receive_pcs1_errdetect[1:0], wire_receive_pcs0_errdetect[1:0]},
		rx_freqlocked = {(wire_receive_pma1_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
		rx_locktodata = {2{1'b0}},
		rx_locktorefclk_wire = {wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
		rx_out_wire = {wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
		rx_patterndetect = {wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
		rx_pcs_rxfound_wire = {txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
		rx_phfifordenable = {2{1'b1}},
		rx_phfiforeset = {2{1'b0}},
		rx_phfifowrdisable = {2{1'b0}},
		rx_pll_pfdrefclkout_wire = {2{wire_pll0_fref}},
		rx_pma_analogtestbus = {{3{1'b0}}, wire_receive_pma1_analogtestbus[6], wire_receive_pma0_analogtestbus[6]},
		rx_pma_clockout = {wire_receive_pma1_clockout, wire_receive_pma0_clockout},
		rx_pma_recoverdataout_wire = {wire_receive_pma1_recoverdataout[9:0], wire_receive_pma0_recoverdataout[9:0]},
		rx_powerdown = {2{1'b0}},
		rx_powerdown_in = {rx_powerdown[1:0]},
		rx_prbscidenable = {2{1'b0}},
		rx_revparallelfdbkdata = {wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
		rx_rmfiforeset = {2{1'b0}},
		rx_signaldetect_wire = {wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
		rx_syncstatus = {wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
		rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
		tx_analogreset_out = {wire_cent_unit0_txanalogresetout[1:0]},
		tx_coreclk_in = {2{coreclkout_wire[0]}},
		tx_datain_wire = {tx_datain[31:0]},
		tx_dataout = {txdataout[1:0]},
		tx_dataout_pcs_to_pma = {wire_transmit_pcs1_dataout[9:0], wire_transmit_pcs0_dataout[9:0]},
		tx_digitalreset_in = {2{tx_digitalreset[0]}},
		tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[1:0]},
		tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
		tx_invpolarity = {2{1'b0}},
		tx_localrefclk = {wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
		tx_pcs_forceelecidleout = {wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
		tx_phfiforeset = {2{1'b0}},
		tx_pipepowerdownout = {wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
		tx_pipepowerstateout = {wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
		tx_pma_fastrefclk0in = {2{wire_pll0_clk[0]}},
		tx_pma_refclk0in = {2{wire_pll0_clk[1]}},
		tx_pma_refclk0inpulse = {2{wire_pll0_clk[2]}},
		tx_revparallellpbken = {2{1'b0}},
		tx_rxdetectvalidout = {wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
		tx_rxfoundout = {wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
		txdataout = {wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
		txdetectrxout = {wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx};
endmodule //altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_02q7
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_3cgx_x2d_gen1_08p (
	cal_blk_clk,
	fixedclk,
	gxb_powerdown,
	pipe8b10binvpolarity,
	pll_inclk,
	powerdn,
	reconfig_clk,
	reconfig_togxb,
	rx_analogreset,
	rx_datain,
	rx_digitalreset,
	tx_ctrlenable,
	tx_datain,
	tx_detectrxloop,
	tx_digitalreset,
	tx_forcedispcompliance,
	tx_forceelecidle,
	coreclkout,
	pipedatavalid,
	pipeelecidle,
	pipephydonestatus,
	pipestatus,
	pll_locked,
	reconfig_fromgxb,
	rx_ctrldetect,
	rx_dataout,
	rx_disperr,
	rx_errdetect,
	rx_freqlocked,
	rx_patterndetect,
	rx_syncstatus,
	tx_dataout)/* synthesis synthesis_clearbox = 2 */;

	input	  cal_blk_clk;
	input	  fixedclk;
	input	[0:0]  gxb_powerdown;
	input	[1:0]  pipe8b10binvpolarity;
	input	  pll_inclk;
	input	[3:0]  powerdn;
	input	  reconfig_clk;
	input	[3:0]  reconfig_togxb;
	input	[0:0]  rx_analogreset;
	input	[1:0]  rx_datain;
	input	[0:0]  rx_digitalreset;
	input	[3:0]  tx_ctrlenable;
	input	[31:0]  tx_datain;
	input	[1:0]  tx_detectrxloop;
	input	[0:0]  tx_digitalreset;
	input	[1:0]  tx_forcedispcompliance;
	input	[1:0]  tx_forceelecidle;
	output	[0:0]  coreclkout;
	output	[1:0]  pipedatavalid;
	output	[1:0]  pipeelecidle;
	output	[1:0]  pipephydonestatus;
	output	[5:0]  pipestatus;
	output	[0:0]  pll_locked;
	output	[4:0]  reconfig_fromgxb;
	output	[3:0]  rx_ctrldetect;
	output	[31:0]  rx_dataout;
	output	[3:0]  rx_disperr;
	output	[3:0]  rx_errdetect;
	output	[1:0]  rx_freqlocked;
	output	[3:0]  rx_patterndetect;
	output	[3:0]  rx_syncstatus;
	output	[1:0]  tx_dataout;

	parameter		starting_channel_number = 0;


	wire [3:0] sub_wire0;
	wire [3:0] sub_wire1;
	wire [0:0] sub_wire2;
	wire [3:0] sub_wire3;
	wire [1:0] sub_wire4;
	wire [3:0] sub_wire5;
	wire [1:0] sub_wire6;
	wire [1:0] sub_wire7;
	wire [1:0] sub_wire8;
	wire [1:0] sub_wire9;
	wire [5:0] sub_wire10;
	wire [3:0] sub_wire11;
	wire [4:0] sub_wire12;
	wire [0:0] sub_wire13;
	wire [31:0] sub_wire14;
	wire [3:0] rx_disperr = sub_wire0[3:0];
	wire [3:0] rx_patterndetect = sub_wire1[3:0];
	wire [0:0] coreclkout = sub_wire2[0:0];
	wire [3:0] rx_ctrldetect = sub_wire3[3:0];
	wire [1:0] pipedatavalid = sub_wire4[1:0];
	wire [3:0] rx_errdetect = sub_wire5[3:0];
	wire [1:0] pipephydonestatus = sub_wire6[1:0];
	wire [1:0] rx_freqlocked = sub_wire7[1:0];
	wire [1:0] tx_dataout = sub_wire8[1:0];
	wire [1:0] pipeelecidle = sub_wire9[1:0];
	wire [5:0] pipestatus = sub_wire10[5:0];
	wire [3:0] rx_syncstatus = sub_wire11[3:0];
	wire [4:0] reconfig_fromgxb = sub_wire12[4:0];
	wire [0:0] pll_locked = sub_wire13[0:0];
	wire [31:0] rx_dataout = sub_wire14[31:0];

	altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_02q7	altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_02q7_component (
				.tx_forceelecidle (tx_forceelecidle),
				.pll_inclk (pll_inclk),
				.gxb_powerdown (gxb_powerdown),
				.tx_datain (tx_datain),
				.cal_blk_clk (cal_blk_clk),
				.powerdn (powerdn),
				.reconfig_clk (reconfig_clk),
				.fixedclk (fixedclk),
				.rx_datain (rx_datain),
				.reconfig_togxb (reconfig_togxb),
				.tx_ctrlenable (tx_ctrlenable),
				.rx_analogreset (rx_analogreset),
				.pipe8b10binvpolarity (pipe8b10binvpolarity),
				.rx_digitalreset (rx_digitalreset),
				.tx_digitalreset (tx_digitalreset),
				.tx_forcedispcompliance (tx_forcedispcompliance),
				.tx_detectrxloop (tx_detectrxloop),
				.rx_disperr (sub_wire0),
				.rx_patterndetect (sub_wire1),
				.coreclkout (sub_wire2),
				.rx_ctrldetect (sub_wire3),
				.pipedatavalid (sub_wire4),
				.rx_errdetect (sub_wire5),
				.pipephydonestatus (sub_wire6),
				.rx_freqlocked (sub_wire7),
				.tx_dataout (sub_wire8),
				.pipeelecidle (sub_wire9),
				.pipestatus (sub_wire10),
				.rx_syncstatus (sub_wire11),
				.reconfig_fromgxb (sub_wire12),
				.pll_locked (sub_wire13),
				.rx_dataout (sub_wire14))/* synthesis synthesis_clearbox=2
	 clearbox_macroname = alt_c3gxb
	 clearbox_defparam = "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=2;operation_mode=duplex;pll_bandwidth_type=High;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x2;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;
	                      rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=x2;tx_channel_width=16;tx_clkout_width=2;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=5;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=2;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_use_external_termination=false;" */;
	defparam
		altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_02q7_component.starting_channel_number = starting_channel_number;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x2"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "18"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x2"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x2"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "5"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "2"
// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "2"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 2 0 INPUT NODEFVAL "pipe8b10binvpolarity[1..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 2 0 OUTPUT NODEFVAL "pipedatavalid[1..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 2 0 OUTPUT NODEFVAL "pipeelecidle[1..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 2 0 OUTPUT NODEFVAL "pipephydonestatus[1..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 6 0 OUTPUT NODEFVAL "pipestatus[5..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 4 0 INPUT NODEFVAL "powerdn[3..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 2 0 INPUT NODEFVAL "rx_datain[1..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 4 0 OUTPUT NODEFVAL "rx_disperr[3..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 4 0 OUTPUT NODEFVAL "rx_errdetect[3..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 2 0 OUTPUT NODEFVAL "rx_freqlocked[1..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 2 0 OUTPUT NODEFVAL "tx_dataout[1..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 2 0 INPUT NODEFVAL "tx_detectrxloop[1..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 2 0 INPUT NODEFVAL "tx_forcedispcompliance[1..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 2 0 INPUT NODEFVAL "tx_forceelecidle[1..0]"
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 2 0 tx_detectrxloop 0 0 2 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 2 0 tx_forcedispcompliance 0 0 2 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
// Retrieval info: CONNECT: pipedatavalid 0 0 2 0 @pipedatavalid 0 0 2 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 4 0 powerdn 0 0 4 0
// Retrieval info: CONNECT: pipeelecidle 0 0 2 0 @pipeelecidle 0 0 2 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: pipestatus 0 0 6 0 @pipestatus 0 0 6 0
// Retrieval info: CONNECT: rx_errdetect 0 0 4 0 @rx_errdetect 0 0 4 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 2 0 pipe8b10binvpolarity 0 0 2 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
// Retrieval info: CONNECT: tx_dataout 0 0 2 0 @tx_dataout 0 0 2 0
// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 2 0 @rx_freqlocked 0 0 2 0
// Retrieval info: CONNECT: @rx_datain 0 0 2 0 rx_datain 0 0 2 0
// Retrieval info: CONNECT: rx_disperr 0 0 4 0 @rx_disperr 0 0 4 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 2 0 @pipephydonestatus 0 0 2 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 2 0 tx_forceelecidle 0 0 2 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneiv_hssi
