q_sys |

2013.03.14.17:25:30 | Datasheet

Overview

clk_0 | q_sys
| pio_led
| out_port
| in_port

All Components
pcie_hard_ip_0 altera_pcie_hard_ip 12.1
onchip_memory2_0 altera_avalon_onchip_memory2 12.1
modular_sgdma_dispatcher_0 modular_sgdma_dispatcher 1.0
pio_led altera_avalon_pio 12.1
pio_pb altera_avalon_pio 12.1
Memory Map

| pcie_hard_ip_0 | dma_read_master_0 | dma_write_master_0
bar1_0 | bar2 | Data_Read_Master | Data_Write_Master
pcie_hard_ip_0 |  |  |  |
txs |  |  | 0x00000000 | 0x00000000
cra |  | 0x00000000 |  |
onchip_memory2_0 |  |  |  |
s1 | 0x07000000 |  | 0x07000000 | 0x07000000
modular_sgdma_dispatcher_0 |  |  |  |
CSR |  | 0x06000000 |  |
Descriptor_Slave |  | 0x06000020 |  |
pio_led |  |  |  |
s1 | 0x04000000 |  |  |
pio_pb |  |  |  |
s1 | 0x04000020 |  |  |

## clk_0

clock_source v12.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pcie_hard_ip_0

altera_pcie_hard_ip v12.1

clk_0 | clk | pcie_hard_ip_0
cal_blk_clk
clk
reconfig_gxbclk
dma_write_master_0 | Data_Write_Master
txs
dma_read_master_0 | Data_Read_Master
txs
|  | pcie_core_clk | modular_sgdma_dispatcher_0
|  | clock
|  | rxm_irq
|  | csr_irq
|  | bar2
|  | CSR
|  | bar2
|  | Descriptor_Slave
|  | pcie_core_clk | dma_read_master_0
|  | Clock
|  | pcie_core_clk | dma_write_master_0
|  | Clock
|  | pcie_core_clk | onchip_memory2_0
|  | clk1
|  | bar1_0
|  | s1
|  | pcie_core_clk | pio_led
|  | clk
|  | bar1_0
|  | s1
|  | pcie_core_clk | pio_pb
|  | clk
|  | bar1_0
|  | s1

## Parameters

under_test | 0
INTENDED_DEVICE_FAMILY | STINGRAY
pcie_qsys | 1
p_pcie_hip_type | 2
lane_mask | 254
my_gen2_lane_rate_mode | false
max_link_width | 1
p_pcie_txrx_clock | 100 MHz
p_pcie_app_clk | 0
millisecond_cycle_count | 125000
core_clk_freq | 1250
p_pcie_test_out_width | 64bits
enable_gen2_core | false
gen2_lane_rate_mode | false
no_soft_reset | false
p_pcie_version | 2.0
core_clk_divider | 2
enable_ch0_pclk_out | true
core_clk_source | pclk
NUM_PREFETCH_MASTERS | 1
CB_P2A_AVALON_ADDR_B0 | 0x00000000
bar0_size_mask | 27
bar0_io_space | false
bar0_64bit_mem_space | true
bar0_prefetchable | true
CB_P2A_AVALON_ADDR_B1 | 0x00000000
bar1_size_mask | 0
bar1_io_space | false
bar1_64bit_mem_space | true
bar1_prefetchable | false
CB_P2A_AVALON_ADDR_B2 | 0x00000000
bar2_size_mask | 27
bar2_io_space | false
bar2_64bit_mem_space | false
bar2_prefetchable | false
CB_P2A_AVALON_ADDR_B3 | 0x00000000
bar3_size_mask | 0
bar3_io_space | false
bar3_64bit_mem_space | false
bar3_prefetchable | false
CB_P2A_AVALON_ADDR_B4 | 0x00000000
bar4_size_mask | 0
bar4_io_space | false
bar4_64bit_mem_space | false
bar4_prefetchable | false
CB_P2A_AVALON_ADDR_B5 | 0x00000000
bar5_size_mask | 0
bar5_io_space | false
bar5_64bit_mem_space | false
bar5_prefetchable | false
fixed_address_mode | 0
CB_P2A_FIXED_AVALON_ADDR_B0 | 0
CB_P2A_FIXED_AVALON_ADDR_B1 | 0
CB_P2A_FIXED_AVALON_ADDR_B2 | 0
CB_P2A_FIXED_AVALON_ADDR_B3 | 0
CB_P2A_FIXED_AVALON_ADDR_B4 | 0
CB_P2A_FIXED_AVALON_ADDR_B5 | 0
BAR | 0,1 - Occupied,2,3,4,5
BAR Type | 64 bit Prefetchable,Not used,32 bit Non-Prefetchable,Not used,Not used,Not used
BAR Size | 27,0,27,0,0,0
Avalon Base Address | 0,0,0,0,0,0
vendor_id | 4466
device_id | 57345
revision_id | 9
class_code | 16711680
subsystem_vendor_id | 4466
subsystem_device_id | 4420
port_link_number | 1
msi_function_count | 0
enable_msi_64bit_addressing | true
enable_function_msix_support | false
eie_before_nfts_count | 4
enable_completion_timeout_disable | false
completion_timeout | NONE
enable_adapter_half_rate_mode | false
msix_pba_bir | 0
msix_pba_offset | 0
msix_table_bir | 0
msix_table_offset | 0
msix_table_size | 0
use_crc_forwarding | false
surprise_down_error_support | false
dll_active_report_support | false
bar_io_window_size | 32BIT
bar_prefetchable | 32
hot_plug_support | 0
no_command_completed | true
slot_power_limit | 0
slot_power_scale | 0
slot_number | 0
enable_slot_register | false
link_common_clock | 1
advanced_errors | false
enable_ecrc_check | false
enable_ecrc_gen | false
my_advanced_errors | false
my_enable_ecrc_check | false
my_enable_ecrc_gen | false
max_payload_size | 1
p_pcie_target_performance_preset | Low
retry_buffer_last_active_address | 255
credit_buffer_allocation_aux | ABSOLUTE
vc0_rx_flow_ctrl_posted_header | 13
vc0_rx_flow_ctrl_posted_data | 107
vc0_rx_flow_ctrl_nonposted_header | 8
vc0_rx_flow_ctrl_nonposted_data | 0
vc0_rx_flow_ctrl_compl_header | 48
vc0_rx_flow_ctrl_compl_data | 256
RX_BUF | 9
RH_NUM | 7
G_TAG_NUM0 | 32
endpoint_l0_latency | 0
endpoint_l1_latency | 0
enable_l1_aspm | false
l01_entry_latency | 31
diffclock_nfts_count | 255
sameclock_nfts_count | 255
l1_exit_latency_sameclock | 7
l1_exit_latency_diffclock | 7
l0_exit_latency_sameclock | 7
l0_exit_latency_diffclock | 7
gen2_diffclock_nfts_count | 255
gen2_sameclock_nfts_count | 255
CG_COMMON_CLOCK_MODE | 1
CB_PCIE_MODE | 0
AST_LITE | 0
CB_PCIE_RX_LITE | 0
CG_RXM_IRQ_NUM | 16
CG_AVALON_S_ADDR_WIDTH | 20
bypass_tl | false
CG_IMPL_CRA_AV_SLAVE_PORT | 1
CG_NO_CPL_REORDERING | 0
CG_ENABLE_A2P_INTERRUPT | 0
CG_IRQ_BIT_ENA | 65535
CB_A2P_ADDR_MAP_IS_FIXED | 0
CB_A2P_ADDR_MAP_NUM_ENTRIES | 2
CB_A2P_ADDR_MAP_PASS_THRU_BITS | 19
CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW | 0
Address Page | 0,1,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
PCIe Address 63:32 | 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
PCIe Address 31:0 | 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
RXM_DATA_WIDTH | 64
RXM_BEN_WIDTH | 8
CB_TXS_ADDRESS_WIDTH | 7
TL_SELECTION | 1
pcie_mode | SHARED_MODE
single_rx_detect | 1
enable_coreclk_out_half_rate | false
low_priority_vc | 0
SLAVE_ADDRESS_MAP_0 | 0
SLAVE_ADDRESS_MAP_1 | 0
SLAVE_ADDRESS_MAP_2 | 27
SLAVE_ADDRESS_MAP_3 | 0
SLAVE_ADDRESS_MAP_4 | 0
SLAVE_ADDRESS_MAP_5 | 0
SLAVE_ADDRESS_MAP_1_0 | 27
SLAVE_ADDRESS_MAP_3_2 | 0
SLAVE_ADDRESS_MAP_5_4 | 0
deviceFamily | STINGRAY
wiz_subprotocol | Gen 1-x1
link_width | 1
cyclone4 | 1
AUTO_CAL_BLK_CLK_CLOCK_RATE | 50000000
AUTO_CAL_BLK_CLK_CLOCK_DOMAIN | 1
AUTO_CAL_BLK_CLK_RESET_DOMAIN | 1
AUTO_DEVICE | EP4CGX22CF19C8
generateLegacySim | false

## Software Assignments

(none)

## onchip_memory2_0

altera_avalon_onchip_memory2 v12.1

pcie_hard_ip_0 | pcie_core_clk | onchip_memory2_0
clk1
bar1_0
s1
clk_0 | clk_reset
reset1
dma_write_master_0 | Data_Write_Master
s1
dma_read_master_0 | Data_Read_Master
s1

## Parameters

allowInSystemMemoryContentEditor | false
autoInitializationFileName | q_sys_onchip_memory2_0
blockType | AUTO
dataWidth | 64
deviceFamily | STINGRAY
dualPort | false
initMemContent | false
initializationFileName | onchip_memory2_0
instanceID | NONE
memorySize | 32768
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
generateLegacySim | false

## Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
INIT_CONTENTS_FILE | "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED | 0
GUI_RAM_BLOCK_TYPE | "Automatic"
WRITABLE | 1
DUAL_PORT | 0
SINGLE_CLOCK_OP | 0
SIZE_VALUE | 32768u
SIZE_MULTIPLE | 1
CONTENTS_INFO | ""
RAM_BLOCK_TYPE | "Auto"
INIT_MEM_CONTENT | 0
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
INSTANCE_ID | "NONE"
READ_DURING_WRITE_MODE | "DONT_CARE"

## modular_sgdma_dispatcher_0

modular_sgdma_dispatcher v1.0

pcie_hard_ip_0 | pcie_core_clk | modular_sgdma_dispatcher_0
clock
rxm_irq
csr_irq
bar2
CSR
bar2
Descriptor_Slave
clk_0 | clk_reset
clock_reset
dma_write_master_0 | Response_Source
Write_Response_Sink
dma_read_master_0 | Response_Source
Read_Response_Sink
|  | Write_Command_Source | dma_write_master_0
|  | Command_Sink
|  | Read_Command_Source | dma_read_master_0
|  | Command_Sink

## Parameters

MODE | 0
GUI_RESPONSE_PORT | 2
RESPONSE_PORT | 2
DESCRIPTOR_FIFO_DEPTH | 8
ENHANCED_FEATURES | 0
DESCRIPTOR_WIDTH | 128
DESCRIPTOR_BYTEENABLE_WIDTH | 16
CSR_ADDRESS_WIDTH | 3
AUTO_CLOCK_CLOCK_RATE | 125000000
AUTO_DEVICE_FAMILY | STINGRAY
deviceFamily | Cyclone IV GX
generateLegacySim | false

## Software Assignments

DESCRIPTOR_FIFO_DEPTH | 8
RESPONSE_FIFO_DEPTH | 16

## dma_read_master_0

dma_read_master v1.0

pcie_hard_ip_0 | pcie_core_clk | dma_read_master_0
Clock
clk_0 | clk_reset
Clock_reset
modular_sgdma_dispatcher_0 | Read_Command_Source
Command_Sink
|  | Response_Source | modular_sgdma_dispatcher_0
|  | Read_Response_Sink
|  | Data_Source | dma_write_master_0
|  | Data_Sink
|  | Data_Read_Master | onchip_memory2_0
|  | s1
|  | Data_Read_Master | pcie_hard_ip_0
|  | txs

## Parameters

DATA_WIDTH | 64
LENGTH_WIDTH | 15
FIFO_DEPTH | 64
STRIDE_ENABLE | 0
GUI_STRIDE_WIDTH | 1
BURST_ENABLE | 1
GUI_MAX_BURST_COUNT | 16
GUI_PROGRAMMABLE_BURST_ENABLE | 0
GUI_BURST_WRAPPING_SUPPORT | 0
TRANSFER_TYPE | Full Word Accesses Only
PACKET_ENABLE | 0
ERROR_ENABLE | 0
ERROR_WIDTH | 8
CHANNEL_ENABLE | 0
CHANNEL_WIDTH | 8
BYTE_ENABLE_WIDTH | 8
BYTE_ENABLE_WIDTH_LOG2 | 3
ADDRESS_WIDTH | 27
FIFO_DEPTH_LOG2 | 6
SYMBOL_WIDTH | 8
NUMBER_OF_SYMBOLS | 8
NUMBER_OF_SYMBOLS_LOG2 | 3
MAX_BURST_COUNT_WIDTH | 5
UNALIGNED_ACCESSES_ENABLE | 0
ONLY_FULL_ACCESS_ENABLE | 1
BURST_WRAPPING_SUPPORT | 0
PROGRAMMABLE_BURST_ENABLE | 0
MAX_BURST_COUNT | 16
FIFO_SPEED_OPTIMIZATION | 1
STRIDE_WIDTH | 1
AUTO_CLOCK_CLOCK_RATE | 125000000
AUTO_DEVICE_FAMILY | STINGRAY
deviceFamily | Cyclone IV GX
generateLegacySim | false

## Software Assignments

(none)

## dma_write_master_0

dma_write_master v1.0

pcie_hard_ip_0 | pcie_core_clk | dma_write_master_0
Clock
clk_0 | clk_reset
Clock_reset
modular_sgdma_dispatcher_0 | Write_Command_Source
Command_Sink
dma_read_master_0 | Data_Source
Data_Sink
|  | Response_Source | modular_sgdma_dispatcher_0
|  | Write_Response_Sink
|  | Data_Write_Master | onchip_memory2_0
|  | s1
|  | Data_Write_Master | pcie_hard_ip_0
|  | txs

## Parameters

DATA_WIDTH | 64
LENGTH_WIDTH | 15
FIFO_DEPTH | 64
STRIDE_ENABLE | 0
GUI_STRIDE_WIDTH | 1
BURST_ENABLE | 1
GUI_MAX_BURST_COUNT | 16
GUI_PROGRAMMABLE_BURST_ENABLE | 0
GUI_BURST_WRAPPING_SUPPORT | 0
TRANSFER_TYPE | Full Word Accesses Only
PACKET_ENABLE | 0
ERROR_ENABLE | 0
ERROR_WIDTH | 8
BYTE_ENABLE_WIDTH | 8
BYTE_ENABLE_WIDTH_LOG2 | 3
ADDRESS_WIDTH | 27
FIFO_DEPTH_LOG2 | 6
SYMBOL_WIDTH | 8
NUMBER_OF_SYMBOLS | 8
NUMBER_OF_SYMBOLS_LOG2 | 3
MAX_BURST_COUNT_WIDTH | 5
UNALIGNED_ACCESSES_ENABLE | 0
ONLY_FULL_ACCESS_ENABLE | 1
BURST_WRAPPING_SUPPORT | 0
PROGRAMMABLE_BURST_ENABLE | 0
MAX_BURST_COUNT | 16
FIFO_SPEED_OPTIMIZATION | 1
STRIDE_WIDTH | 1
ACTUAL_BYTES_TRANSFERRED_WIDTH | 32
AUTO_CLOCK_CLOCK_RATE | 125000000
AUTO_DEVICE_FAMILY | STINGRAY
deviceFamily | Cyclone IV GX
generateLegacySim | false

## Software Assignments

(none)

## pio_led

altera_avalon_pio v12.1

pcie_hard_ip_0 | pcie_core_clk | pio_led
clk
bar1_0
s1
clk_0 | clk_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 3
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## pio_pb

altera_avalon_pio v12.1

pcie_hard_ip_0 | pcie_core_clk | pio_pb
clk
bar1_0
s1
clk_0 | clk_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 2
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

generation took 0.02 seconds | rendering took 0.12 seconds