// q_sys.v

// Generated using ACDS version 12.1sp1 243 at 2013.03.14.17:25:36

`timescale 1 ps / 1 ps
module q_sys (
		input  wire        pcie_hard_ip_0_fixedclk_clk,                       //           pcie_hard_ip_0_fixedclk.clk
		output wire [2:0]  pio_led_out_export,                                //                       pio_led_out.export
		input  wire        pcie_hard_ip_0_pipe_ext_pipe_mode,                 //           pcie_hard_ip_0_pipe_ext.pipe_mode
		input  wire        pcie_hard_ip_0_pipe_ext_phystatus_ext,             //                                  .phystatus_ext
		output wire        pcie_hard_ip_0_pipe_ext_rate_ext,                  //                                  .rate_ext
		output wire [1:0]  pcie_hard_ip_0_pipe_ext_powerdown_ext,             //                                  .powerdown_ext
		output wire        pcie_hard_ip_0_pipe_ext_txdetectrx_ext,            //                                  .txdetectrx_ext
		input  wire        pcie_hard_ip_0_pipe_ext_rxelecidle0_ext,           //                                  .rxelecidle0_ext
		input  wire [7:0]  pcie_hard_ip_0_pipe_ext_rxdata0_ext,               //                                  .rxdata0_ext
		input  wire [2:0]  pcie_hard_ip_0_pipe_ext_rxstatus0_ext,             //                                  .rxstatus0_ext
		input  wire        pcie_hard_ip_0_pipe_ext_rxvalid0_ext,              //                                  .rxvalid0_ext
		input  wire        pcie_hard_ip_0_pipe_ext_rxdatak0_ext,              //                                  .rxdatak0_ext
		output wire [7:0]  pcie_hard_ip_0_pipe_ext_txdata0_ext,               //                                  .txdata0_ext
		output wire        pcie_hard_ip_0_pipe_ext_txdatak0_ext,              //                                  .txdatak0_ext
		output wire        pcie_hard_ip_0_pipe_ext_rxpolarity0_ext,           //                                  .rxpolarity0_ext
		output wire        pcie_hard_ip_0_pipe_ext_txcompl0_ext,              //                                  .txcompl0_ext
		output wire        pcie_hard_ip_0_pipe_ext_txelecidle0_ext,           //                                  .txelecidle0_ext
		input  wire [3:0]  pcie_hard_ip_0_reconfig_togxb_data,                //     pcie_hard_ip_0_reconfig_togxb.data
		input  wire        clk_clk,                                           //                               clk.clk
		input  wire        pcie_hard_ip_0_pcie_rstn_export,                   //          pcie_hard_ip_0_pcie_rstn.export
		input  wire        pcie_hard_ip_0_reconfig_busy_busy_altgxb_reconfig, //      pcie_hard_ip_0_reconfig_busy.busy_altgxb_reconfig
		output wire [63:0] pcie_hard_ip_0_test_out_test_out,                  //           pcie_hard_ip_0_test_out.test_out
		input  wire [1:0]  pio_pb_in_export,                                  //                         pio_pb_in.export
		input  wire        pcie_hard_ip_0_rx_in_rx_datain_0,                  //              pcie_hard_ip_0_rx_in.rx_datain_0
		output wire [4:0]  pcie_hard_ip_0_reconfig_fromgxb_0_data,            // pcie_hard_ip_0_reconfig_fromgxb_0.data
		output wire        pcie_hard_ip_0_tx_out_tx_dataout_0,                //             pcie_hard_ip_0_tx_out.tx_dataout_0
		input  wire        reset_reset_n,                                     //                             reset.reset_n
		output wire        pcie_hard_ip_0_clocks_sim_clk250_export,           //         pcie_hard_ip_0_clocks_sim.clk250_export
		output wire        pcie_hard_ip_0_clocks_sim_clk500_export,           //                                  .clk500_export
		output wire        pcie_hard_ip_0_clocks_sim_clk125_export,           //                                  .clk125_export
		input  wire [39:0] pcie_hard_ip_0_test_in_test_in,                    //            pcie_hard_ip_0_test_in.test_in
		input  wire        pcie_hard_ip_0_refclk_export                       //             pcie_hard_ip_0_refclk.export
	);

	wire          pcie_hard_ip_0_pcie_core_clk_clk;                                                                                 // pcie_hard_ip_0:pcie_core_clk_clk -> [addr_router:clk, addr_router_001:clk, addr_router_002:clk, addr_router_003:clk, agent_pipeline:clk, agent_pipeline_001:clk, agent_pipeline_002:clk, agent_pipeline_003:clk, agent_pipeline_004:clk, agent_pipeline_005:clk, agent_pipeline_006:clk, agent_pipeline_007:clk, agent_pipeline_008:clk, agent_pipeline_009:clk, agent_pipeline_010:clk, agent_pipeline_011:clk, agent_pipeline_012:clk, agent_pipeline_013:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, burst_adapter_003:clk, burst_adapter_004:clk, burst_adapter_005:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_demux_003:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, dma_read_master_0:clk, dma_read_master_0_Data_Read_Master_translator:clk, dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:clk, dma_write_master_0:clk, dma_write_master_0_Data_Write_Master_translator:clk, dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, irq_mapper:clk, irq_synchronizer:receiver_clk, irq_synchronizer:sender_clk, limiter:clk, limiter_001:clk, limiter_002:clk, limiter_pipeline:clk, limiter_pipeline_001:clk, limiter_pipeline_002:clk, limiter_pipeline_003:clk, limiter_pipeline_004:clk, limiter_pipeline_005:clk, modular_sgdma_dispatcher_0:clk, modular_sgdma_dispatcher_0_CSR_translator:clk, modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:clk, modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, modular_sgdma_dispatcher_0_Descriptor_Slave_translator:clk, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:clk, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, mux_pipeline:clk, mux_pipeline_001:clk, mux_pipeline_002:clk, mux_pipeline_003:clk, mux_pipeline_004:clk, mux_pipeline_005:clk, mux_pipeline_006:clk, mux_pipeline_007:clk, mux_pipeline_008:clk, mux_pipeline_009:clk, mux_pipeline_010:clk, mux_pipeline_011:clk, mux_pipeline_012:clk, mux_pipeline_013:clk, mux_pipeline_014:clk, mux_pipeline_015:clk, mux_pipeline_016:clk, mux_pipeline_017:clk, mux_pipeline_018:clk, mux_pipeline_019:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pcie_hard_ip_0_bar1_0_translator:clk, pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:clk, pcie_hard_ip_0_bar2_translator:clk, pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:clk, pcie_hard_ip_0_cra_translator:clk, pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:clk, pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pcie_hard_ip_0_txs_translator:clk, pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:clk, pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pio_led:clk, pio_led_s1_translator:clk, pio_led_s1_translator_avalon_universal_slave_0_agent:clk, pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pio_pb:clk, pio_pb_s1_translator:clk, pio_pb_s1_translator_avalon_universal_slave_0_agent:clk, pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rsp_xbar_mux_002:clk, rsp_xbar_mux_003:clk, rst_controller:clk, rst_controller_001:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk, width_adapter_008:clk, width_adapter_009:clk]
	wire          dma_write_master_0_response_source_valid;                                                                         // dma_write_master_0:src_response_valid -> modular_sgdma_dispatcher_0:snk_write_master_valid
	wire  [255:0] dma_write_master_0_response_source_data;                                                                          // dma_write_master_0:src_response_data -> modular_sgdma_dispatcher_0:snk_write_master_data
	wire          dma_write_master_0_response_source_ready;                                                                         // modular_sgdma_dispatcher_0:snk_write_master_ready -> dma_write_master_0:src_response_ready
	wire          dma_read_master_0_response_source_valid;                                                                          // dma_read_master_0:src_response_valid -> modular_sgdma_dispatcher_0:snk_read_master_valid
	wire  [255:0] dma_read_master_0_response_source_data;                                                                           // dma_read_master_0:src_response_data -> modular_sgdma_dispatcher_0:snk_read_master_data
	wire          dma_read_master_0_response_source_ready;                                                                          // modular_sgdma_dispatcher_0:snk_read_master_ready -> dma_read_master_0:src_response_ready
	wire          modular_sgdma_dispatcher_0_write_command_source_valid;                                                            // modular_sgdma_dispatcher_0:src_write_master_valid -> dma_write_master_0:snk_command_valid
	wire  [255:0] modular_sgdma_dispatcher_0_write_command_source_data;                                                             // modular_sgdma_dispatcher_0:src_write_master_data -> dma_write_master_0:snk_command_data
	wire          modular_sgdma_dispatcher_0_write_command_source_ready;                                                            // dma_write_master_0:snk_command_ready -> modular_sgdma_dispatcher_0:src_write_master_ready
	wire          modular_sgdma_dispatcher_0_read_command_source_valid;                                                             // modular_sgdma_dispatcher_0:src_read_master_valid -> dma_read_master_0:snk_command_valid
	wire  [255:0] modular_sgdma_dispatcher_0_read_command_source_data;                                                              // modular_sgdma_dispatcher_0:src_read_master_data -> dma_read_master_0:snk_command_data
	wire          modular_sgdma_dispatcher_0_read_command_source_ready;                                                             // dma_read_master_0:snk_command_ready -> modular_sgdma_dispatcher_0:src_read_master_ready
	wire          dma_read_master_0_data_source_valid;                                                                              // dma_read_master_0:src_valid -> dma_write_master_0:snk_valid
	wire   [63:0] dma_read_master_0_data_source_data;                                                                               // dma_read_master_0:src_data -> dma_write_master_0:snk_data
	wire          dma_read_master_0_data_source_ready;                                                                              // dma_write_master_0:snk_ready -> dma_read_master_0:src_ready
	wire    [4:0] dma_write_master_0_data_write_master_burstcount;                                                                  // dma_write_master_0:master_burstcount -> dma_write_master_0_Data_Write_Master_translator:av_burstcount
	wire          dma_write_master_0_data_write_master_waitrequest;                                                                 // dma_write_master_0_Data_Write_Master_translator:av_waitrequest -> dma_write_master_0:master_waitrequest
	wire   [63:0] dma_write_master_0_data_write_master_writedata;                                                                   // dma_write_master_0:master_writedata -> dma_write_master_0_Data_Write_Master_translator:av_writedata
	wire   [26:0] dma_write_master_0_data_write_master_address;                                                                     // dma_write_master_0:master_address -> dma_write_master_0_Data_Write_Master_translator:av_address
	wire          dma_write_master_0_data_write_master_write;                                                                       // dma_write_master_0:master_write -> dma_write_master_0_Data_Write_Master_translator:av_write
	wire    [7:0] dma_write_master_0_data_write_master_byteenable;                                                                  // dma_write_master_0:master_byteenable -> dma_write_master_0_Data_Write_Master_translator:av_byteenable
	wire    [4:0] dma_read_master_0_data_read_master_burstcount;                                                                    // dma_read_master_0:master_burstcount -> dma_read_master_0_Data_Read_Master_translator:av_burstcount
	wire          dma_read_master_0_data_read_master_waitrequest;                                                                   // dma_read_master_0_Data_Read_Master_translator:av_waitrequest -> dma_read_master_0:master_waitrequest
	wire   [26:0] dma_read_master_0_data_read_master_address;                                                                       // dma_read_master_0:master_address -> dma_read_master_0_Data_Read_Master_translator:av_address
	wire          dma_read_master_0_data_read_master_read;                                                                          // dma_read_master_0:master_read -> dma_read_master_0_Data_Read_Master_translator:av_read
	wire   [63:0] dma_read_master_0_data_read_master_readdata;                                                                      // dma_read_master_0_Data_Read_Master_translator:av_readdata -> dma_read_master_0:master_readdata
	wire          dma_read_master_0_data_read_master_readdatavalid;                                                                 // dma_read_master_0_Data_Read_Master_translator:av_readdatavalid -> dma_read_master_0:master_readdatavalid
	wire    [7:0] dma_read_master_0_data_read_master_byteenable;                                                                    // dma_read_master_0:master_byteenable -> dma_read_master_0_Data_Read_Master_translator:av_byteenable
	wire    [6:0] pcie_hard_ip_0_bar1_0_burstcount;                                                                                 // pcie_hard_ip_0:bar1_0_burstcount -> pcie_hard_ip_0_bar1_0_translator:av_burstcount
	wire          pcie_hard_ip_0_bar1_0_waitrequest;                                                                                // pcie_hard_ip_0_bar1_0_translator:av_waitrequest -> pcie_hard_ip_0:bar1_0_waitrequest
	wire   [63:0] pcie_hard_ip_0_bar1_0_writedata;                                                                                  // pcie_hard_ip_0:bar1_0_writedata -> pcie_hard_ip_0_bar1_0_translator:av_writedata
	wire   [31:0] pcie_hard_ip_0_bar1_0_address;                                                                                    // pcie_hard_ip_0:bar1_0_address -> pcie_hard_ip_0_bar1_0_translator:av_address
	wire          pcie_hard_ip_0_bar1_0_write;                                                                                      // pcie_hard_ip_0:bar1_0_write -> pcie_hard_ip_0_bar1_0_translator:av_write
	wire          pcie_hard_ip_0_bar1_0_read;                                                                                       // pcie_hard_ip_0:bar1_0_read -> pcie_hard_ip_0_bar1_0_translator:av_read
	wire   [63:0] pcie_hard_ip_0_bar1_0_readdata;                                                                                   // pcie_hard_ip_0_bar1_0_translator:av_readdata -> pcie_hard_ip_0:bar1_0_readdata
	wire    [7:0] pcie_hard_ip_0_bar1_0_byteenable;                                                                                 // pcie_hard_ip_0:bar1_0_byteenable -> pcie_hard_ip_0_bar1_0_translator:av_byteenable
	wire          pcie_hard_ip_0_bar1_0_readdatavalid;                                                                              // pcie_hard_ip_0_bar1_0_translator:av_readdatavalid -> pcie_hard_ip_0:bar1_0_readdatavalid
	wire   [63:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata;                                                     // onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
	wire   [11:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_address;                                                       // onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
	wire          onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect;                                                    // onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
	wire          onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken;                                                         // onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
	wire          onchip_memory2_0_s1_translator_avalon_anti_slave_0_write;                                                         // onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
	wire   [63:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata;                                                      // onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
	wire    [7:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable;                                                    // onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
	wire          pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_waitrequest;                                                    // pcie_hard_ip_0:txs_waitrequest -> pcie_hard_ip_0_txs_translator:av_waitrequest
	wire    [6:0] pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_burstcount;                                                     // pcie_hard_ip_0_txs_translator:av_burstcount -> pcie_hard_ip_0:txs_burstcount
	wire   [63:0] pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_writedata;                                                      // pcie_hard_ip_0_txs_translator:av_writedata -> pcie_hard_ip_0:txs_writedata
	wire   [19:0] pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_address;                                                        // pcie_hard_ip_0_txs_translator:av_address -> pcie_hard_ip_0:txs_address
	wire          pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_chipselect;                                                     // pcie_hard_ip_0_txs_translator:av_chipselect -> pcie_hard_ip_0:txs_chipselect
	wire          pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_write;                                                          // pcie_hard_ip_0_txs_translator:av_write -> pcie_hard_ip_0:txs_write
	wire          pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_read;                                                           // pcie_hard_ip_0_txs_translator:av_read -> pcie_hard_ip_0:txs_read
	wire   [63:0] pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdata;                                                       // pcie_hard_ip_0:txs_readdata -> pcie_hard_ip_0_txs_translator:av_readdata
	wire          pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdatavalid;                                                  // pcie_hard_ip_0:txs_readdatavalid -> pcie_hard_ip_0_txs_translator:av_readdatavalid
	wire    [7:0] pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_byteenable;                                                     // pcie_hard_ip_0_txs_translator:av_byteenable -> pcie_hard_ip_0:txs_byteenable
	wire   [31:0] pio_led_s1_translator_avalon_anti_slave_0_writedata;                                                              // pio_led_s1_translator:av_writedata -> pio_led:writedata
	wire    [1:0] pio_led_s1_translator_avalon_anti_slave_0_address;                                                                // pio_led_s1_translator:av_address -> pio_led:address
	wire          pio_led_s1_translator_avalon_anti_slave_0_chipselect;                                                             // pio_led_s1_translator:av_chipselect -> pio_led:chipselect
	wire          pio_led_s1_translator_avalon_anti_slave_0_write;                                                                  // pio_led_s1_translator:av_write -> pio_led:write_n
	wire   [31:0] pio_led_s1_translator_avalon_anti_slave_0_readdata;                                                               // pio_led:readdata -> pio_led_s1_translator:av_readdata
	wire    [1:0] pio_pb_s1_translator_avalon_anti_slave_0_address;                                                                 // pio_pb_s1_translator:av_address -> pio_pb:address
	wire   [31:0] pio_pb_s1_translator_avalon_anti_slave_0_readdata;                                                                // pio_pb:readdata -> pio_pb_s1_translator:av_readdata
	wire    [6:0] pcie_hard_ip_0_bar2_burstcount;                                                                                   // pcie_hard_ip_0:bar2_burstcount -> pcie_hard_ip_0_bar2_translator:av_burstcount
	wire          pcie_hard_ip_0_bar2_waitrequest;                                                                                  // pcie_hard_ip_0_bar2_translator:av_waitrequest -> pcie_hard_ip_0:bar2_waitrequest
	wire   [63:0] pcie_hard_ip_0_bar2_writedata;                                                                                    // pcie_hard_ip_0:bar2_writedata -> pcie_hard_ip_0_bar2_translator:av_writedata
	wire   [31:0] pcie_hard_ip_0_bar2_address;                                                                                      // pcie_hard_ip_0:bar2_address -> pcie_hard_ip_0_bar2_translator:av_address
	wire          pcie_hard_ip_0_bar2_write;                                                                                        // pcie_hard_ip_0:bar2_write -> pcie_hard_ip_0_bar2_translator:av_write
	wire          pcie_hard_ip_0_bar2_read;                                                                                         // pcie_hard_ip_0:bar2_read -> pcie_hard_ip_0_bar2_translator:av_read
	wire   [63:0] pcie_hard_ip_0_bar2_readdata;                                                                                     // pcie_hard_ip_0_bar2_translator:av_readdata -> pcie_hard_ip_0:bar2_readdata
	wire    [7:0] pcie_hard_ip_0_bar2_byteenable;                                                                                   // pcie_hard_ip_0:bar2_byteenable -> pcie_hard_ip_0_bar2_translator:av_byteenable
	wire          pcie_hard_ip_0_bar2_readdatavalid;                                                                                // pcie_hard_ip_0_bar2_translator:av_readdatavalid -> pcie_hard_ip_0:bar2_readdatavalid
	wire          pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_waitrequest;                                                    // pcie_hard_ip_0:cra_waitrequest -> pcie_hard_ip_0_cra_translator:av_waitrequest
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_writedata;                                                      // pcie_hard_ip_0_cra_translator:av_writedata -> pcie_hard_ip_0:cra_writedata
	wire   [11:0] pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_address;                                                        // pcie_hard_ip_0_cra_translator:av_address -> pcie_hard_ip_0:cra_address
	wire          pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_chipselect;                                                     // pcie_hard_ip_0_cra_translator:av_chipselect -> pcie_hard_ip_0:cra_chipselect
	wire          pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_write;                                                          // pcie_hard_ip_0_cra_translator:av_write -> pcie_hard_ip_0:cra_write
	wire          pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_read;                                                           // pcie_hard_ip_0_cra_translator:av_read -> pcie_hard_ip_0:cra_read
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_readdata;                                                       // pcie_hard_ip_0:cra_readdata -> pcie_hard_ip_0_cra_translator:av_readdata
	wire    [3:0] pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_byteenable;                                                     // pcie_hard_ip_0_cra_translator:av_byteenable -> pcie_hard_ip_0:cra_byteenable
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_writedata;                                          // modular_sgdma_dispatcher_0_CSR_translator:av_writedata -> modular_sgdma_dispatcher_0:csr_writedata
	wire    [2:0] modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_address;                                            // modular_sgdma_dispatcher_0_CSR_translator:av_address -> modular_sgdma_dispatcher_0:csr_address
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_write;                                              // modular_sgdma_dispatcher_0_CSR_translator:av_write -> modular_sgdma_dispatcher_0:csr_write
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_read;                                               // modular_sgdma_dispatcher_0_CSR_translator:av_read -> modular_sgdma_dispatcher_0:csr_read
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_readdata;                                           // modular_sgdma_dispatcher_0:csr_readdata -> modular_sgdma_dispatcher_0_CSR_translator:av_readdata
	wire    [3:0] modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_byteenable;                                         // modular_sgdma_dispatcher_0_CSR_translator:av_byteenable -> modular_sgdma_dispatcher_0:csr_byteenable
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_waitrequest;                           // modular_sgdma_dispatcher_0:descriptor_waitrequest -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:av_waitrequest
	wire  [127:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_writedata;                             // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:av_writedata -> modular_sgdma_dispatcher_0:descriptor_writedata
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_write;                                 // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:av_write -> modular_sgdma_dispatcher_0:descriptor_write
	wire   [15:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_byteenable;                            // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:av_byteenable -> modular_sgdma_dispatcher_0:descriptor_byteenable
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_waitrequest;                            // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_waitrequest -> dma_write_master_0_Data_Write_Master_translator:uav_waitrequest
	wire    [7:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_burstcount;                             // dma_write_master_0_Data_Write_Master_translator:uav_burstcount -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_writedata;                              // dma_write_master_0_Data_Write_Master_translator:uav_writedata -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_address;                                // dma_write_master_0_Data_Write_Master_translator:uav_address -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_address
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_lock;                                   // dma_write_master_0_Data_Write_Master_translator:uav_lock -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_lock
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_write;                                  // dma_write_master_0_Data_Write_Master_translator:uav_write -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_write
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_read;                                   // dma_write_master_0_Data_Write_Master_translator:uav_read -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdata;                               // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_readdata -> dma_write_master_0_Data_Write_Master_translator:uav_readdata
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_debugaccess;                            // dma_write_master_0_Data_Write_Master_translator:uav_debugaccess -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_byteenable;                             // dma_write_master_0_Data_Write_Master_translator:uav_byteenable -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdatavalid;                          // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:av_readdatavalid -> dma_write_master_0_Data_Write_Master_translator:uav_readdatavalid
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_waitrequest;                              // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_waitrequest -> dma_read_master_0_Data_Read_Master_translator:uav_waitrequest
	wire    [7:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_burstcount;                               // dma_read_master_0_Data_Read_Master_translator:uav_burstcount -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_writedata;                                // dma_read_master_0_Data_Read_Master_translator:uav_writedata -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_address;                                  // dma_read_master_0_Data_Read_Master_translator:uav_address -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_address
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_lock;                                     // dma_read_master_0_Data_Read_Master_translator:uav_lock -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_lock
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_write;                                    // dma_read_master_0_Data_Read_Master_translator:uav_write -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_write
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_read;                                     // dma_read_master_0_Data_Read_Master_translator:uav_read -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdata;                                 // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_readdata -> dma_read_master_0_Data_Read_Master_translator:uav_readdata
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_debugaccess;                              // dma_read_master_0_Data_Read_Master_translator:uav_debugaccess -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_byteenable;                               // dma_read_master_0_Data_Read_Master_translator:uav_byteenable -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdatavalid;                            // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:av_readdatavalid -> dma_read_master_0_Data_Read_Master_translator:uav_readdatavalid
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_waitrequest;                                           // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_waitrequest -> pcie_hard_ip_0_bar1_0_translator:uav_waitrequest
	wire    [9:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_burstcount;                                            // pcie_hard_ip_0_bar1_0_translator:uav_burstcount -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_writedata;                                             // pcie_hard_ip_0_bar1_0_translator:uav_writedata -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_address;                                               // pcie_hard_ip_0_bar1_0_translator:uav_address -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_address
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_lock;                                                  // pcie_hard_ip_0_bar1_0_translator:uav_lock -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_lock
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_write;                                                 // pcie_hard_ip_0_bar1_0_translator:uav_write -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_write
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_read;                                                  // pcie_hard_ip_0_bar1_0_translator:uav_read -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdata;                                              // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_readdata -> pcie_hard_ip_0_bar1_0_translator:uav_readdata
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_debugaccess;                                           // pcie_hard_ip_0_bar1_0_translator:uav_debugaccess -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_byteenable;                                            // pcie_hard_ip_0_bar1_0_translator:uav_byteenable -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_byteenable
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdatavalid;                                         // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:av_readdatavalid -> pcie_hard_ip_0_bar1_0_translator:uav_readdatavalid
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                     // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [3:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                      // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
	wire   [63:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                       // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
	wire   [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address;                                         // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write;                                           // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                            // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read;                                            // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
	wire   [63:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                        // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                                   // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                     // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
	wire    [7:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                      // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                              // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                    // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                            // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [153:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                     // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                    // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                           // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                                 // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                         // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [153:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                                  // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                                 // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                               // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [63:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                                // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                               // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                      // pcie_hard_ip_0_txs_translator:uav_waitrequest -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [9:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_burstcount;                                       // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_burstcount -> pcie_hard_ip_0_txs_translator:uav_burstcount
	wire   [63:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_writedata;                                        // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_writedata -> pcie_hard_ip_0_txs_translator:uav_writedata
	wire   [31:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_address;                                          // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_address -> pcie_hard_ip_0_txs_translator:uav_address
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_write;                                            // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_write -> pcie_hard_ip_0_txs_translator:uav_write
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_lock;                                             // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_lock -> pcie_hard_ip_0_txs_translator:uav_lock
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_read;                                             // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_read -> pcie_hard_ip_0_txs_translator:uav_read
	wire   [63:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdata;                                         // pcie_hard_ip_0_txs_translator:uav_readdata -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                                    // pcie_hard_ip_0_txs_translator:uav_readdatavalid -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                      // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pcie_hard_ip_0_txs_translator:uav_debugaccess
	wire    [7:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_byteenable;                                       // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:m0_byteenable -> pcie_hard_ip_0_txs_translator:uav_byteenable
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                               // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_valid;                                     // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_source_valid -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                             // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [153:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_data;                                      // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_source_data -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_ready;                                     // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                            // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                                  // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                          // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [153:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                                   // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                                  // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                                // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [63:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                                 // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                                // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                              // pio_led_s1_translator:uav_waitrequest -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                               // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_led_s1_translator:uav_burstcount
	wire   [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                                // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_led_s1_translator:uav_writedata
	wire   [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address;                                                  // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_led_s1_translator:uav_address
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write;                                                    // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_led_s1_translator:uav_write
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_led_s1_translator:uav_lock
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read;                                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_led_s1_translator:uav_read
	wire   [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                                 // pio_led_s1_translator:uav_readdata -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                                            // pio_led_s1_translator:uav_readdatavalid -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                              // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_led_s1_translator:uav_debugaccess
	wire    [3:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                               // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_led_s1_translator:uav_byteenable
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                                       // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                             // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [117:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                              // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                             // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                                    // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                                          // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                                  // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [117:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                                           // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                                          // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                                        // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                                         // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                                        // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                               // pio_pb_s1_translator:uav_waitrequest -> pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                                // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_pb_s1_translator:uav_burstcount
	wire   [31:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                                 // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_pb_s1_translator:uav_writedata
	wire   [31:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_address;                                                   // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_pb_s1_translator:uav_address
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_write;                                                     // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_pb_s1_translator:uav_write
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                                      // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_pb_s1_translator:uav_lock
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_read;                                                      // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_pb_s1_translator:uav_read
	wire   [31:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                                  // pio_pb_s1_translator:uav_readdata -> pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                                             // pio_pb_s1_translator:uav_readdatavalid -> pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                               // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_pb_s1_translator:uav_debugaccess
	wire    [3:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                                // pio_pb_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_pb_s1_translator:uav_byteenable
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                                        // pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                              // pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                                      // pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [117:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                               // pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                              // pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                                     // pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                                           // pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                                   // pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [117:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                                            // pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                                           // pio_pb_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                                         // pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [31:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                                          // pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                                         // pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_waitrequest;                                             // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_waitrequest -> pcie_hard_ip_0_bar2_translator:uav_waitrequest
	wire    [9:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_burstcount;                                              // pcie_hard_ip_0_bar2_translator:uav_burstcount -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_writedata;                                               // pcie_hard_ip_0_bar2_translator:uav_writedata -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_address;                                                 // pcie_hard_ip_0_bar2_translator:uav_address -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_address
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_lock;                                                    // pcie_hard_ip_0_bar2_translator:uav_lock -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_lock
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_write;                                                   // pcie_hard_ip_0_bar2_translator:uav_write -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_write
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_read;                                                    // pcie_hard_ip_0_bar2_translator:uav_read -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdata;                                                // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_readdata -> pcie_hard_ip_0_bar2_translator:uav_readdata
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_debugaccess;                                             // pcie_hard_ip_0_bar2_translator:uav_debugaccess -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_byteenable;                                              // pcie_hard_ip_0_bar2_translator:uav_byteenable -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_byteenable
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdatavalid;                                           // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:av_readdatavalid -> pcie_hard_ip_0_bar2_translator:uav_readdatavalid
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                      // pcie_hard_ip_0_cra_translator:uav_waitrequest -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_burstcount;                                       // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_burstcount -> pcie_hard_ip_0_cra_translator:uav_burstcount
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_writedata;                                        // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_writedata -> pcie_hard_ip_0_cra_translator:uav_writedata
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_address;                                          // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_address -> pcie_hard_ip_0_cra_translator:uav_address
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_write;                                            // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_write -> pcie_hard_ip_0_cra_translator:uav_write
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_lock;                                             // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_lock -> pcie_hard_ip_0_cra_translator:uav_lock
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_read;                                             // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_read -> pcie_hard_ip_0_cra_translator:uav_read
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdata;                                         // pcie_hard_ip_0_cra_translator:uav_readdata -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                                    // pcie_hard_ip_0_cra_translator:uav_readdatavalid -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                      // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pcie_hard_ip_0_cra_translator:uav_debugaccess
	wire    [3:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_byteenable;                                       // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:m0_byteenable -> pcie_hard_ip_0_cra_translator:uav_byteenable
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                               // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_valid;                                     // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_source_valid -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                             // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [117:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_data;                                      // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_source_data -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_ready;                                     // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                            // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                                  // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                          // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [117:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                                   // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                                  // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                                // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [31:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                                 // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                                // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest;                          // modular_sgdma_dispatcher_0_CSR_translator:uav_waitrequest -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_burstcount;                           // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_burstcount -> modular_sgdma_dispatcher_0_CSR_translator:uav_burstcount
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_writedata;                            // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_writedata -> modular_sgdma_dispatcher_0_CSR_translator:uav_writedata
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_address;                              // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_address -> modular_sgdma_dispatcher_0_CSR_translator:uav_address
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_write;                                // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_write -> modular_sgdma_dispatcher_0_CSR_translator:uav_write
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_lock;                                 // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_lock -> modular_sgdma_dispatcher_0_CSR_translator:uav_lock
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_read;                                 // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_read -> modular_sgdma_dispatcher_0_CSR_translator:uav_read
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdata;                             // modular_sgdma_dispatcher_0_CSR_translator:uav_readdata -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                        // modular_sgdma_dispatcher_0_CSR_translator:uav_readdatavalid -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess;                          // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_debugaccess -> modular_sgdma_dispatcher_0_CSR_translator:uav_debugaccess
	wire    [3:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_byteenable;                           // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:m0_byteenable -> modular_sgdma_dispatcher_0_CSR_translator:uav_byteenable
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                   // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_valid;                         // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_source_valid -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                 // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [117:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_data;                          // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_source_data -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_ready;                         // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                      // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;              // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [117:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                       // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                      // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rf_sink_ready -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                    // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [31:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                     // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                    // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_waitrequest -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [4:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;              // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_burstcount
	wire  [127:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_writedata;               // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_writedata -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_writedata
	wire   [31:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_address;                 // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_address -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_address
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_write;                   // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_write -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_write
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_lock;                    // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_lock -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_lock
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_read;                    // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_read -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_read
	wire  [127:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_readdata -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_readdatavalid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_debugaccess
	wire   [15:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;              // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator:uav_byteenable
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;            // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [225:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_data;             // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_source_data -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;            // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [225:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire  [127:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;       // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [127:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;        // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;       // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                   // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_valid;                         // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                 // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [152:0] dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_data;                          // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire          dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_ready;                         // addr_router:sink_ready -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:cp_ready
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                     // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_valid;                           // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                   // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [152:0] dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_data;                            // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire          dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_ready;                           // addr_router_001:sink_ready -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:cp_ready
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_endofpacket;                                  // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_valid;                                        // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_startofpacket;                                // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
	wire  [152:0] pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_data;                                         // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
	wire          pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_ready;                                        // addr_router_002:sink_ready -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:cp_ready
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_endofpacket;                                    // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_valid;                                          // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_startofpacket;                                  // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
	wire  [152:0] pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_data;                                           // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
	wire          pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_ready;                                          // addr_router_003:sink_ready -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:cp_ready
	wire          addr_router_001_src_endofpacket;                                                                                  // addr_router_001:src_endofpacket -> limiter:cmd_sink_endofpacket
	wire          addr_router_001_src_valid;                                                                                        // addr_router_001:src_valid -> limiter:cmd_sink_valid
	wire          addr_router_001_src_startofpacket;                                                                                // addr_router_001:src_startofpacket -> limiter:cmd_sink_startofpacket
	wire  [152:0] addr_router_001_src_data;                                                                                         // addr_router_001:src_data -> limiter:cmd_sink_data
	wire    [3:0] addr_router_001_src_channel;                                                                                      // addr_router_001:src_channel -> limiter:cmd_sink_channel
	wire          addr_router_001_src_ready;                                                                                        // limiter:cmd_sink_ready -> addr_router_001:src_ready
	wire          limiter_rsp_src_endofpacket;                                                                                      // limiter:rsp_src_endofpacket -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          limiter_rsp_src_valid;                                                                                            // limiter:rsp_src_valid -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_valid
	wire          limiter_rsp_src_startofpacket;                                                                                    // limiter:rsp_src_startofpacket -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [152:0] limiter_rsp_src_data;                                                                                             // limiter:rsp_src_data -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_data
	wire    [3:0] limiter_rsp_src_channel;                                                                                          // limiter:rsp_src_channel -> dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_channel
	wire          limiter_rsp_src_ready;                                                                                            // dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
	wire          addr_router_002_src_endofpacket;                                                                                  // addr_router_002:src_endofpacket -> limiter_001:cmd_sink_endofpacket
	wire          addr_router_002_src_valid;                                                                                        // addr_router_002:src_valid -> limiter_001:cmd_sink_valid
	wire          addr_router_002_src_startofpacket;                                                                                // addr_router_002:src_startofpacket -> limiter_001:cmd_sink_startofpacket
	wire  [152:0] addr_router_002_src_data;                                                                                         // addr_router_002:src_data -> limiter_001:cmd_sink_data
	wire    [3:0] addr_router_002_src_channel;                                                                                      // addr_router_002:src_channel -> limiter_001:cmd_sink_channel
	wire          addr_router_002_src_ready;                                                                                        // limiter_001:cmd_sink_ready -> addr_router_002:src_ready
	wire          limiter_001_rsp_src_endofpacket;                                                                                  // limiter_001:rsp_src_endofpacket -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          limiter_001_rsp_src_valid;                                                                                        // limiter_001:rsp_src_valid -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_valid
	wire          limiter_001_rsp_src_startofpacket;                                                                                // limiter_001:rsp_src_startofpacket -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [152:0] limiter_001_rsp_src_data;                                                                                         // limiter_001:rsp_src_data -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_data
	wire    [3:0] limiter_001_rsp_src_channel;                                                                                      // limiter_001:rsp_src_channel -> pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_channel
	wire          limiter_001_rsp_src_ready;                                                                                        // pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
	wire          addr_router_003_src_endofpacket;                                                                                  // addr_router_003:src_endofpacket -> limiter_002:cmd_sink_endofpacket
	wire          addr_router_003_src_valid;                                                                                        // addr_router_003:src_valid -> limiter_002:cmd_sink_valid
	wire          addr_router_003_src_startofpacket;                                                                                // addr_router_003:src_startofpacket -> limiter_002:cmd_sink_startofpacket
	wire  [152:0] addr_router_003_src_data;                                                                                         // addr_router_003:src_data -> limiter_002:cmd_sink_data
	wire    [2:0] addr_router_003_src_channel;                                                                                      // addr_router_003:src_channel -> limiter_002:cmd_sink_channel
	wire          addr_router_003_src_ready;                                                                                        // limiter_002:cmd_sink_ready -> addr_router_003:src_ready
	wire          limiter_002_rsp_src_endofpacket;                                                                                  // limiter_002:rsp_src_endofpacket -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          limiter_002_rsp_src_valid;                                                                                        // limiter_002:rsp_src_valid -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_valid
	wire          limiter_002_rsp_src_startofpacket;                                                                                // limiter_002:rsp_src_startofpacket -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [152:0] limiter_002_rsp_src_data;                                                                                         // limiter_002:rsp_src_data -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_data
	wire    [2:0] limiter_002_rsp_src_channel;                                                                                      // limiter_002:rsp_src_channel -> pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_channel
	wire          limiter_002_rsp_src_ready;                                                                                        // pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
	wire          rst_controller_reset_out_reset;                                                                                   // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, agent_pipeline:reset, agent_pipeline_001:reset, agent_pipeline_004:reset, agent_pipeline_005:reset, agent_pipeline_006:reset, agent_pipeline_007:reset, agent_pipeline_010:reset, agent_pipeline_011:reset, agent_pipeline_012:reset, agent_pipeline_013:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, burst_adapter_004:reset, burst_adapter_005:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, dma_read_master_0:reset, dma_read_master_0_Data_Read_Master_translator:reset, dma_read_master_0_Data_Read_Master_translator_avalon_universal_master_0_agent:reset, dma_write_master_0:reset, dma_write_master_0_Data_Write_Master_translator:reset, dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:reset, id_router:reset, id_router_002:reset, id_router_003:reset, id_router_005:reset, id_router_006:reset, limiter:reset, limiter_pipeline:reset, limiter_pipeline_001:reset, modular_sgdma_dispatcher_0:reset, modular_sgdma_dispatcher_0_CSR_translator:reset, modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:reset, modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, modular_sgdma_dispatcher_0_Descriptor_Slave_translator:reset, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:reset, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, mux_pipeline:reset, mux_pipeline_001:reset, mux_pipeline_002:reset, mux_pipeline_005:reset, mux_pipeline_006:reset, mux_pipeline_007:reset, mux_pipeline_008:reset, mux_pipeline_009:reset, mux_pipeline_010:reset, mux_pipeline_015:reset, mux_pipeline_016:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_led:reset_n, pio_led_s1_translator:reset, pio_led_s1_translator_avalon_universal_slave_0_agent:reset, pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_pb:reset_n, pio_pb_s1_translator:reset, pio_pb_s1_translator_avalon_universal_slave_0_agent:reset, pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_006:reset, width_adapter_007:reset, width_adapter_008:reset, width_adapter_009:reset]
	wire          rst_controller_001_reset_out_reset;                                                                               // rst_controller_001:reset_out -> [addr_router_002:reset, addr_router_003:reset, agent_pipeline_002:reset, agent_pipeline_003:reset, agent_pipeline_008:reset, agent_pipeline_009:reset, burst_adapter_003:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux_001:reset, id_router_001:reset, id_router_004:reset, limiter_001:reset, limiter_002:reset, limiter_pipeline_002:reset, limiter_pipeline_003:reset, limiter_pipeline_004:reset, limiter_pipeline_005:reset, mux_pipeline_003:reset, mux_pipeline_004:reset, mux_pipeline_011:reset, mux_pipeline_012:reset, mux_pipeline_013:reset, mux_pipeline_014:reset, mux_pipeline_017:reset, mux_pipeline_018:reset, mux_pipeline_019:reset, pcie_hard_ip_0_bar1_0_translator:reset, pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent:reset, pcie_hard_ip_0_bar2_translator:reset, pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent:reset, pcie_hard_ip_0_cra_translator:reset, pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:reset, pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pcie_hard_ip_0_txs_translator:reset, pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:reset, pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_004:reset, rsp_xbar_mux_002:reset, rsp_xbar_mux_003:reset, width_adapter_004:reset, width_adapter_005:reset]
	wire          pcie_hard_ip_0_pcie_core_reset_reset;                                                                             // pcie_hard_ip_0:pcie_core_reset_reset_n -> [irq_mapper:reset, irq_synchronizer:receiver_reset, irq_synchronizer:sender_reset, rst_controller_001:reset_in0]
	wire          addr_router_src_endofpacket;                                                                                      // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          addr_router_src_valid;                                                                                            // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire          addr_router_src_startofpacket;                                                                                    // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [152:0] addr_router_src_data;                                                                                             // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire    [3:0] addr_router_src_channel;                                                                                          // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire          addr_router_src_ready;                                                                                            // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire          rsp_xbar_mux_src_endofpacket;                                                                                     // rsp_xbar_mux:src_endofpacket -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_mux_src_valid;                                                                                           // rsp_xbar_mux:src_valid -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_mux_src_startofpacket;                                                                                   // rsp_xbar_mux:src_startofpacket -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [152:0] rsp_xbar_mux_src_data;                                                                                            // rsp_xbar_mux:src_data -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_data
	wire    [3:0] rsp_xbar_mux_src_channel;                                                                                         // rsp_xbar_mux:src_channel -> dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_mux_src_ready;                                                                                           // dma_write_master_0_Data_Write_Master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                                                     // cmd_xbar_mux:src_endofpacket -> burst_adapter:sink0_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                                           // cmd_xbar_mux:src_valid -> burst_adapter:sink0_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                                                   // cmd_xbar_mux:src_startofpacket -> burst_adapter:sink0_startofpacket
	wire  [152:0] cmd_xbar_mux_src_data;                                                                                            // cmd_xbar_mux:src_data -> burst_adapter:sink0_data
	wire    [3:0] cmd_xbar_mux_src_channel;                                                                                         // cmd_xbar_mux:src_channel -> burst_adapter:sink0_channel
	wire          cmd_xbar_mux_src_ready;                                                                                           // burst_adapter:sink0_ready -> cmd_xbar_mux:src_ready
	wire          id_router_src_endofpacket;                                                                                        // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          id_router_src_valid;                                                                                              // id_router:src_valid -> rsp_xbar_demux:sink_valid
	wire          id_router_src_startofpacket;                                                                                      // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [152:0] id_router_src_data;                                                                                               // id_router:src_data -> rsp_xbar_demux:sink_data
	wire    [3:0] id_router_src_channel;                                                                                            // id_router:src_channel -> rsp_xbar_demux:sink_channel
	wire          id_router_src_ready;                                                                                              // rsp_xbar_demux:sink_ready -> id_router:src_ready
	wire          id_router_001_src_endofpacket;                                                                                    // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire          id_router_001_src_valid;                                                                                          // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
	wire          id_router_001_src_startofpacket;                                                                                  // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [152:0] id_router_001_src_data;                                                                                           // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
	wire    [3:0] id_router_001_src_channel;                                                                                        // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
	wire          id_router_001_src_ready;                                                                                          // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
	wire          mux_pipeline_005_source0_ready;                                                                                   // width_adapter:in_ready -> mux_pipeline_005:out_ready
	wire          width_adapter_src_endofpacket;                                                                                    // width_adapter:out_endofpacket -> burst_adapter_001:sink0_endofpacket
	wire          width_adapter_src_valid;                                                                                          // width_adapter:out_valid -> burst_adapter_001:sink0_valid
	wire          width_adapter_src_startofpacket;                                                                                  // width_adapter:out_startofpacket -> burst_adapter_001:sink0_startofpacket
	wire  [116:0] width_adapter_src_data;                                                                                           // width_adapter:out_data -> burst_adapter_001:sink0_data
	wire          width_adapter_src_ready;                                                                                          // burst_adapter_001:sink0_ready -> width_adapter:out_ready
	wire    [3:0] width_adapter_src_channel;                                                                                        // width_adapter:out_channel -> burst_adapter_001:sink0_channel
	wire          id_router_002_src_endofpacket;                                                                                    // id_router_002:src_endofpacket -> width_adapter_001:in_endofpacket
	wire          id_router_002_src_valid;                                                                                          // id_router_002:src_valid -> width_adapter_001:in_valid
	wire          id_router_002_src_startofpacket;                                                                                  // id_router_002:src_startofpacket -> width_adapter_001:in_startofpacket
	wire  [116:0] id_router_002_src_data;                                                                                           // id_router_002:src_data -> width_adapter_001:in_data
	wire    [3:0] id_router_002_src_channel;                                                                                        // id_router_002:src_channel -> width_adapter_001:in_channel
	wire          id_router_002_src_ready;                                                                                          // width_adapter_001:in_ready -> id_router_002:src_ready
	wire          width_adapter_001_src_endofpacket;                                                                                // width_adapter_001:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
	wire          width_adapter_001_src_valid;                                                                                      // width_adapter_001:out_valid -> rsp_xbar_demux_002:sink_valid
	wire          width_adapter_001_src_startofpacket;                                                                              // width_adapter_001:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
	wire  [152:0] width_adapter_001_src_data;                                                                                       // width_adapter_001:out_data -> rsp_xbar_demux_002:sink_data
	wire          width_adapter_001_src_ready;                                                                                      // rsp_xbar_demux_002:sink_ready -> width_adapter_001:out_ready
	wire    [3:0] width_adapter_001_src_channel;                                                                                    // width_adapter_001:out_channel -> rsp_xbar_demux_002:sink_channel
	wire          mux_pipeline_006_source0_ready;                                                                                   // width_adapter_002:in_ready -> mux_pipeline_006:out_ready
	wire          width_adapter_002_src_endofpacket;                                                                                // width_adapter_002:out_endofpacket -> burst_adapter_002:sink0_endofpacket
	wire          width_adapter_002_src_valid;                                                                                      // width_adapter_002:out_valid -> burst_adapter_002:sink0_valid
	wire          width_adapter_002_src_startofpacket;                                                                              // width_adapter_002:out_startofpacket -> burst_adapter_002:sink0_startofpacket
	wire  [116:0] width_adapter_002_src_data;                                                                                       // width_adapter_002:out_data -> burst_adapter_002:sink0_data
	wire          width_adapter_002_src_ready;                                                                                      // burst_adapter_002:sink0_ready -> width_adapter_002:out_ready
	wire    [3:0] width_adapter_002_src_channel;                                                                                    // width_adapter_002:out_channel -> burst_adapter_002:sink0_channel
	wire          id_router_003_src_endofpacket;                                                                                    // id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
	wire          id_router_003_src_valid;                                                                                          // id_router_003:src_valid -> width_adapter_003:in_valid
	wire          id_router_003_src_startofpacket;                                                                                  // id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
	wire  [116:0] id_router_003_src_data;                                                                                           // id_router_003:src_data -> width_adapter_003:in_data
	wire    [3:0] id_router_003_src_channel;                                                                                        // id_router_003:src_channel -> width_adapter_003:in_channel
	wire          id_router_003_src_ready;                                                                                          // width_adapter_003:in_ready -> id_router_003:src_ready
	wire          width_adapter_003_src_endofpacket;                                                                                // width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
	wire          width_adapter_003_src_valid;                                                                                      // width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
	wire          width_adapter_003_src_startofpacket;                                                                              // width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
	wire  [152:0] width_adapter_003_src_data;                                                                                       // width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
	wire          width_adapter_003_src_ready;                                                                                      // rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
	wire    [3:0] width_adapter_003_src_channel;                                                                                    // width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
	wire          mux_pipeline_014_source0_ready;                                                                                   // width_adapter_004:in_ready -> mux_pipeline_014:out_ready
	wire          width_adapter_004_src_endofpacket;                                                                                // width_adapter_004:out_endofpacket -> burst_adapter_003:sink0_endofpacket
	wire          width_adapter_004_src_valid;                                                                                      // width_adapter_004:out_valid -> burst_adapter_003:sink0_valid
	wire          width_adapter_004_src_startofpacket;                                                                              // width_adapter_004:out_startofpacket -> burst_adapter_003:sink0_startofpacket
	wire  [116:0] width_adapter_004_src_data;                                                                                       // width_adapter_004:out_data -> burst_adapter_003:sink0_data
	wire          width_adapter_004_src_ready;                                                                                      // burst_adapter_003:sink0_ready -> width_adapter_004:out_ready
	wire    [2:0] width_adapter_004_src_channel;                                                                                    // width_adapter_004:out_channel -> burst_adapter_003:sink0_channel
	wire          id_router_004_src_endofpacket;                                                                                    // id_router_004:src_endofpacket -> width_adapter_005:in_endofpacket
	wire          id_router_004_src_valid;                                                                                          // id_router_004:src_valid -> width_adapter_005:in_valid
	wire          id_router_004_src_startofpacket;                                                                                  // id_router_004:src_startofpacket -> width_adapter_005:in_startofpacket
	wire  [116:0] id_router_004_src_data;                                                                                           // id_router_004:src_data -> width_adapter_005:in_data
	wire    [2:0] id_router_004_src_channel;                                                                                        // id_router_004:src_channel -> width_adapter_005:in_channel
	wire          id_router_004_src_ready;                                                                                          // width_adapter_005:in_ready -> id_router_004:src_ready
	wire          width_adapter_005_src_endofpacket;                                                                                // width_adapter_005:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
	wire          width_adapter_005_src_valid;                                                                                      // width_adapter_005:out_valid -> rsp_xbar_demux_004:sink_valid
	wire          width_adapter_005_src_startofpacket;                                                                              // width_adapter_005:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
	wire  [152:0] width_adapter_005_src_data;                                                                                       // width_adapter_005:out_data -> rsp_xbar_demux_004:sink_data
	wire          width_adapter_005_src_ready;                                                                                      // rsp_xbar_demux_004:sink_ready -> width_adapter_005:out_ready
	wire    [2:0] width_adapter_005_src_channel;                                                                                    // width_adapter_005:out_channel -> rsp_xbar_demux_004:sink_channel
	wire          mux_pipeline_015_source0_ready;                                                                                   // width_adapter_006:in_ready -> mux_pipeline_015:out_ready
	wire          width_adapter_006_src_endofpacket;                                                                                // width_adapter_006:out_endofpacket -> burst_adapter_004:sink0_endofpacket
	wire          width_adapter_006_src_valid;                                                                                      // width_adapter_006:out_valid -> burst_adapter_004:sink0_valid
	wire          width_adapter_006_src_startofpacket;                                                                              // width_adapter_006:out_startofpacket -> burst_adapter_004:sink0_startofpacket
	wire  [116:0] width_adapter_006_src_data;                                                                                       // width_adapter_006:out_data -> burst_adapter_004:sink0_data
	wire          width_adapter_006_src_ready;                                                                                      // burst_adapter_004:sink0_ready -> width_adapter_006:out_ready
	wire    [2:0] width_adapter_006_src_channel;                                                                                    // width_adapter_006:out_channel -> burst_adapter_004:sink0_channel
	wire          id_router_005_src_endofpacket;                                                                                    // id_router_005:src_endofpacket -> width_adapter_007:in_endofpacket
	wire          id_router_005_src_valid;                                                                                          // id_router_005:src_valid -> width_adapter_007:in_valid
	wire          id_router_005_src_startofpacket;                                                                                  // id_router_005:src_startofpacket -> width_adapter_007:in_startofpacket
	wire  [116:0] id_router_005_src_data;                                                                                           // id_router_005:src_data -> width_adapter_007:in_data
	wire    [2:0] id_router_005_src_channel;                                                                                        // id_router_005:src_channel -> width_adapter_007:in_channel
	wire          id_router_005_src_ready;                                                                                          // width_adapter_007:in_ready -> id_router_005:src_ready
	wire          width_adapter_007_src_endofpacket;                                                                                // width_adapter_007:out_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
	wire          width_adapter_007_src_valid;                                                                                      // width_adapter_007:out_valid -> rsp_xbar_demux_005:sink_valid
	wire          width_adapter_007_src_startofpacket;                                                                              // width_adapter_007:out_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
	wire  [152:0] width_adapter_007_src_data;                                                                                       // width_adapter_007:out_data -> rsp_xbar_demux_005:sink_data
	wire          width_adapter_007_src_ready;                                                                                      // rsp_xbar_demux_005:sink_ready -> width_adapter_007:out_ready
	wire    [2:0] width_adapter_007_src_channel;                                                                                    // width_adapter_007:out_channel -> rsp_xbar_demux_005:sink_channel
	wire          mux_pipeline_016_source0_ready;                                                                                   // width_adapter_008:in_ready -> mux_pipeline_016:out_ready
	wire          width_adapter_008_src_endofpacket;                                                                                // width_adapter_008:out_endofpacket -> burst_adapter_005:sink0_endofpacket
	wire          width_adapter_008_src_valid;                                                                                      // width_adapter_008:out_valid -> burst_adapter_005:sink0_valid
	wire          width_adapter_008_src_startofpacket;                                                                              // width_adapter_008:out_startofpacket -> burst_adapter_005:sink0_startofpacket
	wire  [224:0] width_adapter_008_src_data;                                                                                       // width_adapter_008:out_data -> burst_adapter_005:sink0_data
	wire          width_adapter_008_src_ready;                                                                                      // burst_adapter_005:sink0_ready -> width_adapter_008:out_ready
	wire    [2:0] width_adapter_008_src_channel;                                                                                    // width_adapter_008:out_channel -> burst_adapter_005:sink0_channel
	wire          id_router_006_src_endofpacket;                                                                                    // id_router_006:src_endofpacket -> width_adapter_009:in_endofpacket
	wire          id_router_006_src_valid;                                                                                          // id_router_006:src_valid -> width_adapter_009:in_valid
	wire          id_router_006_src_startofpacket;                                                                                  // id_router_006:src_startofpacket -> width_adapter_009:in_startofpacket
	wire  [224:0] id_router_006_src_data;                                                                                           // id_router_006:src_data -> width_adapter_009:in_data
	wire    [2:0] id_router_006_src_channel;                                                                                        // id_router_006:src_channel -> width_adapter_009:in_channel
	wire          id_router_006_src_ready;                                                                                          // width_adapter_009:in_ready -> id_router_006:src_ready
	wire          width_adapter_009_src_endofpacket;                                                                                // width_adapter_009:out_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
	wire          width_adapter_009_src_valid;                                                                                      // width_adapter_009:out_valid -> rsp_xbar_demux_006:sink_valid
	wire          width_adapter_009_src_startofpacket;                                                                              // width_adapter_009:out_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
	wire  [152:0] width_adapter_009_src_data;                                                                                       // width_adapter_009:out_data -> rsp_xbar_demux_006:sink_data
	wire          width_adapter_009_src_ready;                                                                                      // rsp_xbar_demux_006:sink_ready -> width_adapter_009:out_ready
	wire    [2:0] width_adapter_009_src_channel;                                                                                    // width_adapter_009:out_channel -> rsp_xbar_demux_006:sink_channel
	wire          limiter_pipeline_source0_endofpacket;                                                                             // limiter_pipeline:out_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          limiter_pipeline_source0_valid;                                                                                   // limiter_pipeline:out_valid -> cmd_xbar_demux_001:sink_valid
	wire          limiter_pipeline_source0_startofpacket;                                                                           // limiter_pipeline:out_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [152:0] limiter_pipeline_source0_data;                                                                                    // limiter_pipeline:out_data -> cmd_xbar_demux_001:sink_data
	wire    [3:0] limiter_pipeline_source0_channel;                                                                                 // limiter_pipeline:out_channel -> cmd_xbar_demux_001:sink_channel
	wire          limiter_pipeline_source0_ready;                                                                                   // cmd_xbar_demux_001:sink_ready -> limiter_pipeline:out_ready
	wire          limiter_cmd_src_endofpacket;                                                                                      // limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire    [0:0] limiter_cmd_src_valid;                                                                                            // limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire          limiter_cmd_src_startofpacket;                                                                                    // limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire  [152:0] limiter_cmd_src_data;                                                                                             // limiter:cmd_src_data -> limiter_pipeline:in_data
	wire    [3:0] limiter_cmd_src_channel;                                                                                          // limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          limiter_cmd_src_ready;                                                                                            // limiter_pipeline:in_ready -> limiter:cmd_src_ready
	wire          rsp_xbar_mux_001_src_endofpacket;                                                                                 // rsp_xbar_mux_001:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          rsp_xbar_mux_001_src_valid;                                                                                       // rsp_xbar_mux_001:src_valid -> limiter_pipeline_001:in_valid
	wire          rsp_xbar_mux_001_src_startofpacket;                                                                               // rsp_xbar_mux_001:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire  [152:0] rsp_xbar_mux_001_src_data;                                                                                        // rsp_xbar_mux_001:src_data -> limiter_pipeline_001:in_data
	wire    [3:0] rsp_xbar_mux_001_src_channel;                                                                                     // rsp_xbar_mux_001:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_xbar_mux_001_src_ready;                                                                                       // limiter_pipeline_001:in_ready -> rsp_xbar_mux_001:src_ready
	wire          limiter_pipeline_001_source0_endofpacket;                                                                         // limiter_pipeline_001:out_endofpacket -> limiter:rsp_sink_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                                                               // limiter_pipeline_001:out_valid -> limiter:rsp_sink_valid
	wire          limiter_pipeline_001_source0_startofpacket;                                                                       // limiter_pipeline_001:out_startofpacket -> limiter:rsp_sink_startofpacket
	wire  [152:0] limiter_pipeline_001_source0_data;                                                                                // limiter_pipeline_001:out_data -> limiter:rsp_sink_data
	wire    [3:0] limiter_pipeline_001_source0_channel;                                                                             // limiter_pipeline_001:out_channel -> limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_ready;                                                                               // limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire          limiter_pipeline_002_source0_endofpacket;                                                                         // limiter_pipeline_002:out_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
	wire          limiter_pipeline_002_source0_valid;                                                                               // limiter_pipeline_002:out_valid -> cmd_xbar_demux_002:sink_valid
	wire          limiter_pipeline_002_source0_startofpacket;                                                                       // limiter_pipeline_002:out_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
	wire  [152:0] limiter_pipeline_002_source0_data;                                                                                // limiter_pipeline_002:out_data -> cmd_xbar_demux_002:sink_data
	wire    [3:0] limiter_pipeline_002_source0_channel;                                                                             // limiter_pipeline_002:out_channel -> cmd_xbar_demux_002:sink_channel
	wire          limiter_pipeline_002_source0_ready;                                                                               // cmd_xbar_demux_002:sink_ready -> limiter_pipeline_002:out_ready
	wire          limiter_001_cmd_src_endofpacket;                                                                                  // limiter_001:cmd_src_endofpacket -> limiter_pipeline_002:in_endofpacket
	wire    [0:0] limiter_001_cmd_src_valid;                                                                                        // limiter_001:cmd_src_valid -> limiter_pipeline_002:in_valid
	wire          limiter_001_cmd_src_startofpacket;                                                                                // limiter_001:cmd_src_startofpacket -> limiter_pipeline_002:in_startofpacket
	wire  [152:0] limiter_001_cmd_src_data;                                                                                         // limiter_001:cmd_src_data -> limiter_pipeline_002:in_data
	wire    [3:0] limiter_001_cmd_src_channel;                                                                                      // limiter_001:cmd_src_channel -> limiter_pipeline_002:in_channel
	wire          limiter_001_cmd_src_ready;                                                                                        // limiter_pipeline_002:in_ready -> limiter_001:cmd_src_ready
	wire          rsp_xbar_mux_002_src_endofpacket;                                                                                 // rsp_xbar_mux_002:src_endofpacket -> limiter_pipeline_003:in_endofpacket
	wire          rsp_xbar_mux_002_src_valid;                                                                                       // rsp_xbar_mux_002:src_valid -> limiter_pipeline_003:in_valid
	wire          rsp_xbar_mux_002_src_startofpacket;                                                                               // rsp_xbar_mux_002:src_startofpacket -> limiter_pipeline_003:in_startofpacket
	wire  [152:0] rsp_xbar_mux_002_src_data;                                                                                        // rsp_xbar_mux_002:src_data -> limiter_pipeline_003:in_data
	wire    [3:0] rsp_xbar_mux_002_src_channel;                                                                                     // rsp_xbar_mux_002:src_channel -> limiter_pipeline_003:in_channel
	wire          rsp_xbar_mux_002_src_ready;                                                                                       // limiter_pipeline_003:in_ready -> rsp_xbar_mux_002:src_ready
	wire          limiter_pipeline_003_source0_endofpacket;                                                                         // limiter_pipeline_003:out_endofpacket -> limiter_001:rsp_sink_endofpacket
	wire          limiter_pipeline_003_source0_valid;                                                                               // limiter_pipeline_003:out_valid -> limiter_001:rsp_sink_valid
	wire          limiter_pipeline_003_source0_startofpacket;                                                                       // limiter_pipeline_003:out_startofpacket -> limiter_001:rsp_sink_startofpacket
	wire  [152:0] limiter_pipeline_003_source0_data;                                                                                // limiter_pipeline_003:out_data -> limiter_001:rsp_sink_data
	wire    [3:0] limiter_pipeline_003_source0_channel;                                                                             // limiter_pipeline_003:out_channel -> limiter_001:rsp_sink_channel
	wire          limiter_pipeline_003_source0_ready;                                                                               // limiter_001:rsp_sink_ready -> limiter_pipeline_003:out_ready
	wire          limiter_pipeline_004_source0_endofpacket;                                                                         // limiter_pipeline_004:out_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
	wire          limiter_pipeline_004_source0_valid;                                                                               // limiter_pipeline_004:out_valid -> cmd_xbar_demux_003:sink_valid
	wire          limiter_pipeline_004_source0_startofpacket;                                                                       // limiter_pipeline_004:out_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
	wire  [152:0] limiter_pipeline_004_source0_data;                                                                                // limiter_pipeline_004:out_data -> cmd_xbar_demux_003:sink_data
	wire    [2:0] limiter_pipeline_004_source0_channel;                                                                             // limiter_pipeline_004:out_channel -> cmd_xbar_demux_003:sink_channel
	wire          limiter_pipeline_004_source0_ready;                                                                               // cmd_xbar_demux_003:sink_ready -> limiter_pipeline_004:out_ready
	wire          limiter_002_cmd_src_endofpacket;                                                                                  // limiter_002:cmd_src_endofpacket -> limiter_pipeline_004:in_endofpacket
	wire    [0:0] limiter_002_cmd_src_valid;                                                                                        // limiter_002:cmd_src_valid -> limiter_pipeline_004:in_valid
	wire          limiter_002_cmd_src_startofpacket;                                                                                // limiter_002:cmd_src_startofpacket -> limiter_pipeline_004:in_startofpacket
	wire  [152:0] limiter_002_cmd_src_data;                                                                                         // limiter_002:cmd_src_data -> limiter_pipeline_004:in_data
	wire    [2:0] limiter_002_cmd_src_channel;                                                                                      // limiter_002:cmd_src_channel -> limiter_pipeline_004:in_channel
	wire          limiter_002_cmd_src_ready;                                                                                        // limiter_pipeline_004:in_ready -> limiter_002:cmd_src_ready
	wire          rsp_xbar_mux_003_src_endofpacket;                                                                                 // rsp_xbar_mux_003:src_endofpacket -> limiter_pipeline_005:in_endofpacket
	wire          rsp_xbar_mux_003_src_valid;                                                                                       // rsp_xbar_mux_003:src_valid -> limiter_pipeline_005:in_valid
	wire          rsp_xbar_mux_003_src_startofpacket;                                                                               // rsp_xbar_mux_003:src_startofpacket -> limiter_pipeline_005:in_startofpacket
	wire  [152:0] rsp_xbar_mux_003_src_data;                                                                                        // rsp_xbar_mux_003:src_data -> limiter_pipeline_005:in_data
	wire    [2:0] rsp_xbar_mux_003_src_channel;                                                                                     // rsp_xbar_mux_003:src_channel -> limiter_pipeline_005:in_channel
	wire          rsp_xbar_mux_003_src_ready;                                                                                       // limiter_pipeline_005:in_ready -> rsp_xbar_mux_003:src_ready
	wire          limiter_pipeline_005_source0_endofpacket;                                                                         // limiter_pipeline_005:out_endofpacket -> limiter_002:rsp_sink_endofpacket
	wire          limiter_pipeline_005_source0_valid;                                                                               // limiter_pipeline_005:out_valid -> limiter_002:rsp_sink_valid
	wire          limiter_pipeline_005_source0_startofpacket;                                                                       // limiter_pipeline_005:out_startofpacket -> limiter_002:rsp_sink_startofpacket
	wire  [152:0] limiter_pipeline_005_source0_data;                                                                                // limiter_pipeline_005:out_data -> limiter_002:rsp_sink_data
	wire    [2:0] limiter_pipeline_005_source0_channel;                                                                             // limiter_pipeline_005:out_channel -> limiter_002:rsp_sink_channel
	wire          limiter_pipeline_005_source0_ready;                                                                               // limiter_002:rsp_sink_ready -> limiter_pipeline_005:out_ready
	wire          burst_adapter_source0_endofpacket;                                                                                // burst_adapter:source0_endofpacket -> agent_pipeline:in_endofpacket
	wire          burst_adapter_source0_valid;                                                                                      // burst_adapter:source0_valid -> agent_pipeline:in_valid
	wire          burst_adapter_source0_startofpacket;                                                                              // burst_adapter:source0_startofpacket -> agent_pipeline:in_startofpacket
	wire  [152:0] burst_adapter_source0_data;                                                                                       // burst_adapter:source0_data -> agent_pipeline:in_data
	wire          burst_adapter_source0_ready;                                                                                      // agent_pipeline:in_ready -> burst_adapter:source0_ready
	wire    [3:0] burst_adapter_source0_channel;                                                                                    // burst_adapter:source0_channel -> agent_pipeline:in_channel
	wire          agent_pipeline_source0_endofpacket;                                                                               // agent_pipeline:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_source0_valid;                                                                                     // agent_pipeline:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_source0_startofpacket;                                                                             // agent_pipeline:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [152:0] agent_pipeline_source0_data;                                                                                      // agent_pipeline:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire    [3:0] agent_pipeline_source0_channel;                                                                                   // agent_pipeline:out_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_source0_ready;                                                                                     // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline:out_ready
	wire          agent_pipeline_001_source0_endofpacket;                                                                           // agent_pipeline_001:out_endofpacket -> id_router:sink_endofpacket
	wire          agent_pipeline_001_source0_valid;                                                                                 // agent_pipeline_001:out_valid -> id_router:sink_valid
	wire          agent_pipeline_001_source0_startofpacket;                                                                         // agent_pipeline_001:out_startofpacket -> id_router:sink_startofpacket
	wire  [152:0] agent_pipeline_001_source0_data;                                                                                  // agent_pipeline_001:out_data -> id_router:sink_data
	wire          agent_pipeline_001_source0_ready;                                                                                 // id_router:sink_ready -> agent_pipeline_001:out_ready
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                     // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                           // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_001:in_valid
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                                   // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire  [152:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data;                                            // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_001:in_data
	wire          onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                           // agent_pipeline_001:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          cmd_xbar_mux_001_src_endofpacket;                                                                                 // cmd_xbar_mux_001:src_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          cmd_xbar_mux_001_src_valid;                                                                                       // cmd_xbar_mux_001:src_valid -> agent_pipeline_002:in_valid
	wire          cmd_xbar_mux_001_src_startofpacket;                                                                               // cmd_xbar_mux_001:src_startofpacket -> agent_pipeline_002:in_startofpacket
	wire  [152:0] cmd_xbar_mux_001_src_data;                                                                                        // cmd_xbar_mux_001:src_data -> agent_pipeline_002:in_data
	wire    [3:0] cmd_xbar_mux_001_src_channel;                                                                                     // cmd_xbar_mux_001:src_channel -> agent_pipeline_002:in_channel
	wire          cmd_xbar_mux_001_src_ready;                                                                                       // agent_pipeline_002:in_ready -> cmd_xbar_mux_001:src_ready
	wire          agent_pipeline_002_source0_endofpacket;                                                                           // agent_pipeline_002:out_endofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_002_source0_valid;                                                                                 // agent_pipeline_002:out_valid -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_002_source0_startofpacket;                                                                         // agent_pipeline_002:out_startofpacket -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [152:0] agent_pipeline_002_source0_data;                                                                                  // agent_pipeline_002:out_data -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_data
	wire    [3:0] agent_pipeline_002_source0_channel;                                                                               // agent_pipeline_002:out_channel -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_002_source0_ready;                                                                                 // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_002:out_ready
	wire          agent_pipeline_003_source0_endofpacket;                                                                           // agent_pipeline_003:out_endofpacket -> id_router_001:sink_endofpacket
	wire          agent_pipeline_003_source0_valid;                                                                                 // agent_pipeline_003:out_valid -> id_router_001:sink_valid
	wire          agent_pipeline_003_source0_startofpacket;                                                                         // agent_pipeline_003:out_startofpacket -> id_router_001:sink_startofpacket
	wire  [152:0] agent_pipeline_003_source0_data;                                                                                  // agent_pipeline_003:out_data -> id_router_001:sink_data
	wire          agent_pipeline_003_source0_ready;                                                                                 // id_router_001:sink_ready -> agent_pipeline_003:out_ready
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                      // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_valid;                                            // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_003:in_valid
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_startofpacket;                                    // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire  [152:0] pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_data;                                             // pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_003:in_data
	wire          pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_ready;                                            // agent_pipeline_003:in_ready -> pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_001_source0_endofpacket;                                                                            // burst_adapter_001:source0_endofpacket -> agent_pipeline_004:in_endofpacket
	wire          burst_adapter_001_source0_valid;                                                                                  // burst_adapter_001:source0_valid -> agent_pipeline_004:in_valid
	wire          burst_adapter_001_source0_startofpacket;                                                                          // burst_adapter_001:source0_startofpacket -> agent_pipeline_004:in_startofpacket
	wire  [116:0] burst_adapter_001_source0_data;                                                                                   // burst_adapter_001:source0_data -> agent_pipeline_004:in_data
	wire          burst_adapter_001_source0_ready;                                                                                  // agent_pipeline_004:in_ready -> burst_adapter_001:source0_ready
	wire    [3:0] burst_adapter_001_source0_channel;                                                                                // burst_adapter_001:source0_channel -> agent_pipeline_004:in_channel
	wire          agent_pipeline_004_source0_endofpacket;                                                                           // agent_pipeline_004:out_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_004_source0_valid;                                                                                 // agent_pipeline_004:out_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_004_source0_startofpacket;                                                                         // agent_pipeline_004:out_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [116:0] agent_pipeline_004_source0_data;                                                                                  // agent_pipeline_004:out_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire    [3:0] agent_pipeline_004_source0_channel;                                                                               // agent_pipeline_004:out_channel -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_004_source0_ready;                                                                                 // pio_led_s1_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_004:out_ready
	wire          agent_pipeline_005_source0_endofpacket;                                                                           // agent_pipeline_005:out_endofpacket -> id_router_002:sink_endofpacket
	wire          agent_pipeline_005_source0_valid;                                                                                 // agent_pipeline_005:out_valid -> id_router_002:sink_valid
	wire          agent_pipeline_005_source0_startofpacket;                                                                         // agent_pipeline_005:out_startofpacket -> id_router_002:sink_startofpacket
	wire  [116:0] agent_pipeline_005_source0_data;                                                                                  // agent_pipeline_005:out_data -> id_router_002:sink_data
	wire          agent_pipeline_005_source0_ready;                                                                                 // id_router_002:sink_ready -> agent_pipeline_005:out_ready
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                              // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_005:in_endofpacket
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                                    // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_005:in_valid
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                                            // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_005:in_startofpacket
	wire  [116:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data;                                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_005:in_data
	wire          pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                                    // agent_pipeline_005:in_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_002_source0_endofpacket;                                                                            // burst_adapter_002:source0_endofpacket -> agent_pipeline_006:in_endofpacket
	wire          burst_adapter_002_source0_valid;                                                                                  // burst_adapter_002:source0_valid -> agent_pipeline_006:in_valid
	wire          burst_adapter_002_source0_startofpacket;                                                                          // burst_adapter_002:source0_startofpacket -> agent_pipeline_006:in_startofpacket
	wire  [116:0] burst_adapter_002_source0_data;                                                                                   // burst_adapter_002:source0_data -> agent_pipeline_006:in_data
	wire          burst_adapter_002_source0_ready;                                                                                  // agent_pipeline_006:in_ready -> burst_adapter_002:source0_ready
	wire    [3:0] burst_adapter_002_source0_channel;                                                                                // burst_adapter_002:source0_channel -> agent_pipeline_006:in_channel
	wire          agent_pipeline_006_source0_endofpacket;                                                                           // agent_pipeline_006:out_endofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_006_source0_valid;                                                                                 // agent_pipeline_006:out_valid -> pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_006_source0_startofpacket;                                                                         // agent_pipeline_006:out_startofpacket -> pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [116:0] agent_pipeline_006_source0_data;                                                                                  // agent_pipeline_006:out_data -> pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire    [3:0] agent_pipeline_006_source0_channel;                                                                               // agent_pipeline_006:out_channel -> pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_006_source0_ready;                                                                                 // pio_pb_s1_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_006:out_ready
	wire          agent_pipeline_007_source0_endofpacket;                                                                           // agent_pipeline_007:out_endofpacket -> id_router_003:sink_endofpacket
	wire          agent_pipeline_007_source0_valid;                                                                                 // agent_pipeline_007:out_valid -> id_router_003:sink_valid
	wire          agent_pipeline_007_source0_startofpacket;                                                                         // agent_pipeline_007:out_startofpacket -> id_router_003:sink_startofpacket
	wire  [116:0] agent_pipeline_007_source0_data;                                                                                  // agent_pipeline_007:out_data -> id_router_003:sink_data
	wire          agent_pipeline_007_source0_ready;                                                                                 // id_router_003:sink_ready -> agent_pipeline_007:out_ready
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                               // pio_pb_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_007:in_endofpacket
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                                     // pio_pb_s1_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_007:in_valid
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                                             // pio_pb_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_007:in_startofpacket
	wire  [116:0] pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_data;                                                      // pio_pb_s1_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_007:in_data
	wire          pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                                     // agent_pipeline_007:in_ready -> pio_pb_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_003_source0_endofpacket;                                                                            // burst_adapter_003:source0_endofpacket -> agent_pipeline_008:in_endofpacket
	wire          burst_adapter_003_source0_valid;                                                                                  // burst_adapter_003:source0_valid -> agent_pipeline_008:in_valid
	wire          burst_adapter_003_source0_startofpacket;                                                                          // burst_adapter_003:source0_startofpacket -> agent_pipeline_008:in_startofpacket
	wire  [116:0] burst_adapter_003_source0_data;                                                                                   // burst_adapter_003:source0_data -> agent_pipeline_008:in_data
	wire          burst_adapter_003_source0_ready;                                                                                  // agent_pipeline_008:in_ready -> burst_adapter_003:source0_ready
	wire    [2:0] burst_adapter_003_source0_channel;                                                                                // burst_adapter_003:source0_channel -> agent_pipeline_008:in_channel
	wire          agent_pipeline_008_source0_endofpacket;                                                                           // agent_pipeline_008:out_endofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_008_source0_valid;                                                                                 // agent_pipeline_008:out_valid -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_008_source0_startofpacket;                                                                         // agent_pipeline_008:out_startofpacket -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [116:0] agent_pipeline_008_source0_data;                                                                                  // agent_pipeline_008:out_data -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_data
	wire    [2:0] agent_pipeline_008_source0_channel;                                                                               // agent_pipeline_008:out_channel -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_008_source0_ready;                                                                                 // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_008:out_ready
	wire          agent_pipeline_009_source0_endofpacket;                                                                           // agent_pipeline_009:out_endofpacket -> id_router_004:sink_endofpacket
	wire          agent_pipeline_009_source0_valid;                                                                                 // agent_pipeline_009:out_valid -> id_router_004:sink_valid
	wire          agent_pipeline_009_source0_startofpacket;                                                                         // agent_pipeline_009:out_startofpacket -> id_router_004:sink_startofpacket
	wire  [116:0] agent_pipeline_009_source0_data;                                                                                  // agent_pipeline_009:out_data -> id_router_004:sink_data
	wire          agent_pipeline_009_source0_ready;                                                                                 // id_router_004:sink_ready -> agent_pipeline_009:out_ready
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                      // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_009:in_endofpacket
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_valid;                                            // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_009:in_valid
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_startofpacket;                                    // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_009:in_startofpacket
	wire  [116:0] pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_data;                                             // pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_009:in_data
	wire          pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_ready;                                            // agent_pipeline_009:in_ready -> pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_004_source0_endofpacket;                                                                            // burst_adapter_004:source0_endofpacket -> agent_pipeline_010:in_endofpacket
	wire          burst_adapter_004_source0_valid;                                                                                  // burst_adapter_004:source0_valid -> agent_pipeline_010:in_valid
	wire          burst_adapter_004_source0_startofpacket;                                                                          // burst_adapter_004:source0_startofpacket -> agent_pipeline_010:in_startofpacket
	wire  [116:0] burst_adapter_004_source0_data;                                                                                   // burst_adapter_004:source0_data -> agent_pipeline_010:in_data
	wire          burst_adapter_004_source0_ready;                                                                                  // agent_pipeline_010:in_ready -> burst_adapter_004:source0_ready
	wire    [2:0] burst_adapter_004_source0_channel;                                                                                // burst_adapter_004:source0_channel -> agent_pipeline_010:in_channel
	wire          agent_pipeline_010_source0_endofpacket;                                                                           // agent_pipeline_010:out_endofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_010_source0_valid;                                                                                 // agent_pipeline_010:out_valid -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_010_source0_startofpacket;                                                                         // agent_pipeline_010:out_startofpacket -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [116:0] agent_pipeline_010_source0_data;                                                                                  // agent_pipeline_010:out_data -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_data
	wire    [2:0] agent_pipeline_010_source0_channel;                                                                               // agent_pipeline_010:out_channel -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_010_source0_ready;                                                                                 // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_010:out_ready
	wire          agent_pipeline_011_source0_endofpacket;                                                                           // agent_pipeline_011:out_endofpacket -> id_router_005:sink_endofpacket
	wire          agent_pipeline_011_source0_valid;                                                                                 // agent_pipeline_011:out_valid -> id_router_005:sink_valid
	wire          agent_pipeline_011_source0_startofpacket;                                                                         // agent_pipeline_011:out_startofpacket -> id_router_005:sink_startofpacket
	wire  [116:0] agent_pipeline_011_source0_data;                                                                                  // agent_pipeline_011:out_data -> id_router_005:sink_data
	wire          agent_pipeline_011_source0_ready;                                                                                 // id_router_005:sink_ready -> agent_pipeline_011:out_ready
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket;                          // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_011:in_endofpacket
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_valid;                                // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_011:in_valid
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket;                        // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_011:in_startofpacket
	wire  [116:0] modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_data;                                 // modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_011:in_data
	wire          modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_ready;                                // agent_pipeline_011:in_ready -> modular_sgdma_dispatcher_0_CSR_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_005_source0_endofpacket;                                                                            // burst_adapter_005:source0_endofpacket -> agent_pipeline_012:in_endofpacket
	wire          burst_adapter_005_source0_valid;                                                                                  // burst_adapter_005:source0_valid -> agent_pipeline_012:in_valid
	wire          burst_adapter_005_source0_startofpacket;                                                                          // burst_adapter_005:source0_startofpacket -> agent_pipeline_012:in_startofpacket
	wire  [224:0] burst_adapter_005_source0_data;                                                                                   // burst_adapter_005:source0_data -> agent_pipeline_012:in_data
	wire          burst_adapter_005_source0_ready;                                                                                  // agent_pipeline_012:in_ready -> burst_adapter_005:source0_ready
	wire    [2:0] burst_adapter_005_source0_channel;                                                                                // burst_adapter_005:source0_channel -> agent_pipeline_012:in_channel
	wire          agent_pipeline_012_source0_endofpacket;                                                                           // agent_pipeline_012:out_endofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          agent_pipeline_012_source0_valid;                                                                                 // agent_pipeline_012:out_valid -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_valid
	wire          agent_pipeline_012_source0_startofpacket;                                                                         // agent_pipeline_012:out_startofpacket -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [224:0] agent_pipeline_012_source0_data;                                                                                  // agent_pipeline_012:out_data -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_data
	wire    [2:0] agent_pipeline_012_source0_channel;                                                                               // agent_pipeline_012:out_channel -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_channel
	wire          agent_pipeline_012_source0_ready;                                                                                 // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:cp_ready -> agent_pipeline_012:out_ready
	wire          agent_pipeline_013_source0_endofpacket;                                                                           // agent_pipeline_013:out_endofpacket -> id_router_006:sink_endofpacket
	wire          agent_pipeline_013_source0_valid;                                                                                 // agent_pipeline_013:out_valid -> id_router_006:sink_valid
	wire          agent_pipeline_013_source0_startofpacket;                                                                         // agent_pipeline_013:out_startofpacket -> id_router_006:sink_startofpacket
	wire  [224:0] agent_pipeline_013_source0_data;                                                                                  // agent_pipeline_013:out_data -> id_router_006:sink_data
	wire          agent_pipeline_013_source0_ready;                                                                                 // id_router_006:sink_ready -> agent_pipeline_013:out_ready
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> agent_pipeline_013:in_endofpacket
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_valid;                   // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rp_valid -> agent_pipeline_013:in_valid
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> agent_pipeline_013:in_startofpacket
	wire  [224:0] modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_data;                    // modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rp_data -> agent_pipeline_013:in_data
	wire          modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_ready;                   // agent_pipeline_013:in_ready -> modular_sgdma_dispatcher_0_Descriptor_Slave_translator_avalon_universal_slave_0_agent:rp_ready
	wire          cmd_xbar_demux_src0_endofpacket;                                                                                  // cmd_xbar_demux:src0_endofpacket -> mux_pipeline:in_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                                                        // cmd_xbar_demux:src0_valid -> mux_pipeline:in_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                                                // cmd_xbar_demux:src0_startofpacket -> mux_pipeline:in_startofpacket
	wire  [152:0] cmd_xbar_demux_src0_data;                                                                                         // cmd_xbar_demux:src0_data -> mux_pipeline:in_data
	wire    [3:0] cmd_xbar_demux_src0_channel;                                                                                      // cmd_xbar_demux:src0_channel -> mux_pipeline:in_channel
	wire          cmd_xbar_demux_src0_ready;                                                                                        // mux_pipeline:in_ready -> cmd_xbar_demux:src0_ready
	wire          mux_pipeline_source0_endofpacket;                                                                                 // mux_pipeline:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          mux_pipeline_source0_valid;                                                                                       // mux_pipeline:out_valid -> cmd_xbar_mux:sink0_valid
	wire          mux_pipeline_source0_startofpacket;                                                                               // mux_pipeline:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [152:0] mux_pipeline_source0_data;                                                                                        // mux_pipeline:out_data -> cmd_xbar_mux:sink0_data
	wire    [3:0] mux_pipeline_source0_channel;                                                                                     // mux_pipeline:out_channel -> cmd_xbar_mux:sink0_channel
	wire          mux_pipeline_source0_ready;                                                                                       // cmd_xbar_mux:sink0_ready -> mux_pipeline:out_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                                              // cmd_xbar_demux_001:src0_endofpacket -> mux_pipeline_001:in_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                                                    // cmd_xbar_demux_001:src0_valid -> mux_pipeline_001:in_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                                            // cmd_xbar_demux_001:src0_startofpacket -> mux_pipeline_001:in_startofpacket
	wire  [152:0] cmd_xbar_demux_001_src0_data;                                                                                     // cmd_xbar_demux_001:src0_data -> mux_pipeline_001:in_data
	wire    [3:0] cmd_xbar_demux_001_src0_channel;                                                                                  // cmd_xbar_demux_001:src0_channel -> mux_pipeline_001:in_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                                                    // mux_pipeline_001:in_ready -> cmd_xbar_demux_001:src0_ready
	wire          mux_pipeline_001_source0_endofpacket;                                                                             // mux_pipeline_001:out_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire          mux_pipeline_001_source0_valid;                                                                                   // mux_pipeline_001:out_valid -> cmd_xbar_mux:sink1_valid
	wire          mux_pipeline_001_source0_startofpacket;                                                                           // mux_pipeline_001:out_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire  [152:0] mux_pipeline_001_source0_data;                                                                                    // mux_pipeline_001:out_data -> cmd_xbar_mux:sink1_data
	wire    [3:0] mux_pipeline_001_source0_channel;                                                                                 // mux_pipeline_001:out_channel -> cmd_xbar_mux:sink1_channel
	wire          mux_pipeline_001_source0_ready;                                                                                   // cmd_xbar_mux:sink1_ready -> mux_pipeline_001:out_ready
	wire          cmd_xbar_demux_002_src0_endofpacket;                                                                              // cmd_xbar_demux_002:src0_endofpacket -> mux_pipeline_002:in_endofpacket
	wire          cmd_xbar_demux_002_src0_valid;                                                                                    // cmd_xbar_demux_002:src0_valid -> mux_pipeline_002:in_valid
	wire          cmd_xbar_demux_002_src0_startofpacket;                                                                            // cmd_xbar_demux_002:src0_startofpacket -> mux_pipeline_002:in_startofpacket
	wire  [152:0] cmd_xbar_demux_002_src0_data;                                                                                     // cmd_xbar_demux_002:src0_data -> mux_pipeline_002:in_data
	wire    [3:0] cmd_xbar_demux_002_src0_channel;                                                                                  // cmd_xbar_demux_002:src0_channel -> mux_pipeline_002:in_channel
	wire          cmd_xbar_demux_002_src0_ready;                                                                                    // mux_pipeline_002:in_ready -> cmd_xbar_demux_002:src0_ready
	wire          mux_pipeline_002_source0_endofpacket;                                                                             // mux_pipeline_002:out_endofpacket -> cmd_xbar_mux:sink2_endofpacket
	wire          mux_pipeline_002_source0_valid;                                                                                   // mux_pipeline_002:out_valid -> cmd_xbar_mux:sink2_valid
	wire          mux_pipeline_002_source0_startofpacket;                                                                           // mux_pipeline_002:out_startofpacket -> cmd_xbar_mux:sink2_startofpacket
	wire  [152:0] mux_pipeline_002_source0_data;                                                                                    // mux_pipeline_002:out_data -> cmd_xbar_mux:sink2_data
	wire    [3:0] mux_pipeline_002_source0_channel;                                                                                 // mux_pipeline_002:out_channel -> cmd_xbar_mux:sink2_channel
	wire          mux_pipeline_002_source0_ready;                                                                                   // cmd_xbar_mux:sink2_ready -> mux_pipeline_002:out_ready
	wire          cmd_xbar_demux_src1_endofpacket;                                                                                  // cmd_xbar_demux:src1_endofpacket -> mux_pipeline_003:in_endofpacket
	wire          cmd_xbar_demux_src1_valid;                                                                                        // cmd_xbar_demux:src1_valid -> mux_pipeline_003:in_valid
	wire          cmd_xbar_demux_src1_startofpacket;                                                                                // cmd_xbar_demux:src1_startofpacket -> mux_pipeline_003:in_startofpacket
	wire  [152:0] cmd_xbar_demux_src1_data;                                                                                         // cmd_xbar_demux:src1_data -> mux_pipeline_003:in_data
	wire    [3:0] cmd_xbar_demux_src1_channel;                                                                                      // cmd_xbar_demux:src1_channel -> mux_pipeline_003:in_channel
	wire          cmd_xbar_demux_src1_ready;                                                                                        // mux_pipeline_003:in_ready -> cmd_xbar_demux:src1_ready
	wire          mux_pipeline_003_source0_endofpacket;                                                                             // mux_pipeline_003:out_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
	wire          mux_pipeline_003_source0_valid;                                                                                   // mux_pipeline_003:out_valid -> cmd_xbar_mux_001:sink0_valid
	wire          mux_pipeline_003_source0_startofpacket;                                                                           // mux_pipeline_003:out_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
	wire  [152:0] mux_pipeline_003_source0_data;                                                                                    // mux_pipeline_003:out_data -> cmd_xbar_mux_001:sink0_data
	wire    [3:0] mux_pipeline_003_source0_channel;                                                                                 // mux_pipeline_003:out_channel -> cmd_xbar_mux_001:sink0_channel
	wire          mux_pipeline_003_source0_ready;                                                                                   // cmd_xbar_mux_001:sink0_ready -> mux_pipeline_003:out_ready
	wire          cmd_xbar_demux_001_src1_endofpacket;                                                                              // cmd_xbar_demux_001:src1_endofpacket -> mux_pipeline_004:in_endofpacket
	wire          cmd_xbar_demux_001_src1_valid;                                                                                    // cmd_xbar_demux_001:src1_valid -> mux_pipeline_004:in_valid
	wire          cmd_xbar_demux_001_src1_startofpacket;                                                                            // cmd_xbar_demux_001:src1_startofpacket -> mux_pipeline_004:in_startofpacket
	wire  [152:0] cmd_xbar_demux_001_src1_data;                                                                                     // cmd_xbar_demux_001:src1_data -> mux_pipeline_004:in_data
	wire    [3:0] cmd_xbar_demux_001_src1_channel;                                                                                  // cmd_xbar_demux_001:src1_channel -> mux_pipeline_004:in_channel
	wire          cmd_xbar_demux_001_src1_ready;                                                                                    // mux_pipeline_004:in_ready -> cmd_xbar_demux_001:src1_ready
	wire          mux_pipeline_004_source0_endofpacket;                                                                             // mux_pipeline_004:out_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
	wire          mux_pipeline_004_source0_valid;                                                                                   // mux_pipeline_004:out_valid -> cmd_xbar_mux_001:sink1_valid
	wire          mux_pipeline_004_source0_startofpacket;                                                                           // mux_pipeline_004:out_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
	wire  [152:0] mux_pipeline_004_source0_data;                                                                                    // mux_pipeline_004:out_data -> cmd_xbar_mux_001:sink1_data
	wire    [3:0] mux_pipeline_004_source0_channel;                                                                                 // mux_pipeline_004:out_channel -> cmd_xbar_mux_001:sink1_channel
	wire          mux_pipeline_004_source0_ready;                                                                                   // cmd_xbar_mux_001:sink1_ready -> mux_pipeline_004:out_ready
	wire          cmd_xbar_demux_002_src1_endofpacket;                                                                              // cmd_xbar_demux_002:src1_endofpacket -> mux_pipeline_005:in_endofpacket
	wire          cmd_xbar_demux_002_src1_valid;                                                                                    // cmd_xbar_demux_002:src1_valid -> mux_pipeline_005:in_valid
	wire          cmd_xbar_demux_002_src1_startofpacket;                                                                            // cmd_xbar_demux_002:src1_startofpacket -> mux_pipeline_005:in_startofpacket
	wire  [152:0] cmd_xbar_demux_002_src1_data;                                                                                     // cmd_xbar_demux_002:src1_data -> mux_pipeline_005:in_data
	wire    [3:0] cmd_xbar_demux_002_src1_channel;                                                                                  // cmd_xbar_demux_002:src1_channel -> mux_pipeline_005:in_channel
	wire          cmd_xbar_demux_002_src1_ready;                                                                                    // mux_pipeline_005:in_ready -> cmd_xbar_demux_002:src1_ready
	wire          mux_pipeline_005_source0_endofpacket;                                                                             // mux_pipeline_005:out_endofpacket -> width_adapter:in_endofpacket
	wire          mux_pipeline_005_source0_valid;                                                                                   // mux_pipeline_005:out_valid -> width_adapter:in_valid
	wire          mux_pipeline_005_source0_startofpacket;                                                                           // mux_pipeline_005:out_startofpacket -> width_adapter:in_startofpacket
	wire  [152:0] mux_pipeline_005_source0_data;                                                                                    // mux_pipeline_005:out_data -> width_adapter:in_data
	wire    [3:0] mux_pipeline_005_source0_channel;                                                                                 // mux_pipeline_005:out_channel -> width_adapter:in_channel
	wire          cmd_xbar_demux_002_src2_endofpacket;                                                                              // cmd_xbar_demux_002:src2_endofpacket -> mux_pipeline_006:in_endofpacket
	wire          cmd_xbar_demux_002_src2_valid;                                                                                    // cmd_xbar_demux_002:src2_valid -> mux_pipeline_006:in_valid
	wire          cmd_xbar_demux_002_src2_startofpacket;                                                                            // cmd_xbar_demux_002:src2_startofpacket -> mux_pipeline_006:in_startofpacket
	wire  [152:0] cmd_xbar_demux_002_src2_data;                                                                                     // cmd_xbar_demux_002:src2_data -> mux_pipeline_006:in_data
	wire    [3:0] cmd_xbar_demux_002_src2_channel;                                                                                  // cmd_xbar_demux_002:src2_channel -> mux_pipeline_006:in_channel
	wire          cmd_xbar_demux_002_src2_ready;                                                                                    // mux_pipeline_006:in_ready -> cmd_xbar_demux_002:src2_ready
	wire          mux_pipeline_006_source0_endofpacket;                                                                             // mux_pipeline_006:out_endofpacket -> width_adapter_002:in_endofpacket
	wire          mux_pipeline_006_source0_valid;                                                                                   // mux_pipeline_006:out_valid -> width_adapter_002:in_valid
	wire          mux_pipeline_006_source0_startofpacket;                                                                           // mux_pipeline_006:out_startofpacket -> width_adapter_002:in_startofpacket
	wire  [152:0] mux_pipeline_006_source0_data;                                                                                    // mux_pipeline_006:out_data -> width_adapter_002:in_data
	wire    [3:0] mux_pipeline_006_source0_channel;                                                                                 // mux_pipeline_006:out_channel -> width_adapter_002:in_channel
	wire          rsp_xbar_demux_src0_endofpacket;                                                                                  // rsp_xbar_demux:src0_endofpacket -> mux_pipeline_007:in_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                                                        // rsp_xbar_demux:src0_valid -> mux_pipeline_007:in_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                                                // rsp_xbar_demux:src0_startofpacket -> mux_pipeline_007:in_startofpacket
	wire  [152:0] rsp_xbar_demux_src0_data;                                                                                         // rsp_xbar_demux:src0_data -> mux_pipeline_007:in_data
	wire    [3:0] rsp_xbar_demux_src0_channel;                                                                                      // rsp_xbar_demux:src0_channel -> mux_pipeline_007:in_channel
	wire          rsp_xbar_demux_src0_ready;                                                                                        // mux_pipeline_007:in_ready -> rsp_xbar_demux:src0_ready
	wire          mux_pipeline_007_source0_endofpacket;                                                                             // mux_pipeline_007:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire          mux_pipeline_007_source0_valid;                                                                                   // mux_pipeline_007:out_valid -> rsp_xbar_mux:sink0_valid
	wire          mux_pipeline_007_source0_startofpacket;                                                                           // mux_pipeline_007:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [152:0] mux_pipeline_007_source0_data;                                                                                    // mux_pipeline_007:out_data -> rsp_xbar_mux:sink0_data
	wire    [3:0] mux_pipeline_007_source0_channel;                                                                                 // mux_pipeline_007:out_channel -> rsp_xbar_mux:sink0_channel
	wire          mux_pipeline_007_source0_ready;                                                                                   // rsp_xbar_mux:sink0_ready -> mux_pipeline_007:out_ready
	wire          rsp_xbar_demux_001_src0_endofpacket;                                                                              // rsp_xbar_demux_001:src0_endofpacket -> mux_pipeline_008:in_endofpacket
	wire          rsp_xbar_demux_001_src0_valid;                                                                                    // rsp_xbar_demux_001:src0_valid -> mux_pipeline_008:in_valid
	wire          rsp_xbar_demux_001_src0_startofpacket;                                                                            // rsp_xbar_demux_001:src0_startofpacket -> mux_pipeline_008:in_startofpacket
	wire  [152:0] rsp_xbar_demux_001_src0_data;                                                                                     // rsp_xbar_demux_001:src0_data -> mux_pipeline_008:in_data
	wire    [3:0] rsp_xbar_demux_001_src0_channel;                                                                                  // rsp_xbar_demux_001:src0_channel -> mux_pipeline_008:in_channel
	wire          rsp_xbar_demux_001_src0_ready;                                                                                    // mux_pipeline_008:in_ready -> rsp_xbar_demux_001:src0_ready
	wire          mux_pipeline_008_source0_endofpacket;                                                                             // mux_pipeline_008:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire          mux_pipeline_008_source0_valid;                                                                                   // mux_pipeline_008:out_valid -> rsp_xbar_mux:sink1_valid
	wire          mux_pipeline_008_source0_startofpacket;                                                                           // mux_pipeline_008:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [152:0] mux_pipeline_008_source0_data;                                                                                    // mux_pipeline_008:out_data -> rsp_xbar_mux:sink1_data
	wire    [3:0] mux_pipeline_008_source0_channel;                                                                                 // mux_pipeline_008:out_channel -> rsp_xbar_mux:sink1_channel
	wire          mux_pipeline_008_source0_ready;                                                                                   // rsp_xbar_mux:sink1_ready -> mux_pipeline_008:out_ready
	wire          rsp_xbar_demux_src1_endofpacket;                                                                                  // rsp_xbar_demux:src1_endofpacket -> mux_pipeline_009:in_endofpacket
	wire          rsp_xbar_demux_src1_valid;                                                                                        // rsp_xbar_demux:src1_valid -> mux_pipeline_009:in_valid
	wire          rsp_xbar_demux_src1_startofpacket;                                                                                // rsp_xbar_demux:src1_startofpacket -> mux_pipeline_009:in_startofpacket
	wire  [152:0] rsp_xbar_demux_src1_data;                                                                                         // rsp_xbar_demux:src1_data -> mux_pipeline_009:in_data
	wire    [3:0] rsp_xbar_demux_src1_channel;                                                                                      // rsp_xbar_demux:src1_channel -> mux_pipeline_009:in_channel
	wire          rsp_xbar_demux_src1_ready;                                                                                        // mux_pipeline_009:in_ready -> rsp_xbar_demux:src1_ready
	wire          mux_pipeline_009_source0_endofpacket;                                                                             // mux_pipeline_009:out_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
	wire          mux_pipeline_009_source0_valid;                                                                                   // mux_pipeline_009:out_valid -> rsp_xbar_mux_001:sink0_valid
	wire          mux_pipeline_009_source0_startofpacket;                                                                           // mux_pipeline_009:out_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
	wire  [152:0] mux_pipeline_009_source0_data;                                                                                    // mux_pipeline_009:out_data -> rsp_xbar_mux_001:sink0_data
	wire    [3:0] mux_pipeline_009_source0_channel;                                                                                 // mux_pipeline_009:out_channel -> rsp_xbar_mux_001:sink0_channel
	wire          mux_pipeline_009_source0_ready;                                                                                   // rsp_xbar_mux_001:sink0_ready -> mux_pipeline_009:out_ready
	wire          rsp_xbar_demux_001_src1_endofpacket;                                                                              // rsp_xbar_demux_001:src1_endofpacket -> mux_pipeline_010:in_endofpacket
	wire          rsp_xbar_demux_001_src1_valid;                                                                                    // rsp_xbar_demux_001:src1_valid -> mux_pipeline_010:in_valid
	wire          rsp_xbar_demux_001_src1_startofpacket;                                                                            // rsp_xbar_demux_001:src1_startofpacket -> mux_pipeline_010:in_startofpacket
	wire  [152:0] rsp_xbar_demux_001_src1_data;                                                                                     // rsp_xbar_demux_001:src1_data -> mux_pipeline_010:in_data
	wire    [3:0] rsp_xbar_demux_001_src1_channel;                                                                                  // rsp_xbar_demux_001:src1_channel -> mux_pipeline_010:in_channel
	wire          rsp_xbar_demux_001_src1_ready;                                                                                    // mux_pipeline_010:in_ready -> rsp_xbar_demux_001:src1_ready
	wire          mux_pipeline_010_source0_endofpacket;                                                                             // mux_pipeline_010:out_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
	wire          mux_pipeline_010_source0_valid;                                                                                   // mux_pipeline_010:out_valid -> rsp_xbar_mux_001:sink1_valid
	wire          mux_pipeline_010_source0_startofpacket;                                                                           // mux_pipeline_010:out_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
	wire  [152:0] mux_pipeline_010_source0_data;                                                                                    // mux_pipeline_010:out_data -> rsp_xbar_mux_001:sink1_data
	wire    [3:0] mux_pipeline_010_source0_channel;                                                                                 // mux_pipeline_010:out_channel -> rsp_xbar_mux_001:sink1_channel
	wire          mux_pipeline_010_source0_ready;                                                                                   // rsp_xbar_mux_001:sink1_ready -> mux_pipeline_010:out_ready
	wire          rsp_xbar_demux_src2_endofpacket;                                                                                  // rsp_xbar_demux:src2_endofpacket -> mux_pipeline_011:in_endofpacket
	wire          rsp_xbar_demux_src2_valid;                                                                                        // rsp_xbar_demux:src2_valid -> mux_pipeline_011:in_valid
	wire          rsp_xbar_demux_src2_startofpacket;                                                                                // rsp_xbar_demux:src2_startofpacket -> mux_pipeline_011:in_startofpacket
	wire  [152:0] rsp_xbar_demux_src2_data;                                                                                         // rsp_xbar_demux:src2_data -> mux_pipeline_011:in_data
	wire    [3:0] rsp_xbar_demux_src2_channel;                                                                                      // rsp_xbar_demux:src2_channel -> mux_pipeline_011:in_channel
	wire          rsp_xbar_demux_src2_ready;                                                                                        // mux_pipeline_011:in_ready -> rsp_xbar_demux:src2_ready
	wire          mux_pipeline_011_source0_endofpacket;                                                                             // mux_pipeline_011:out_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
	wire          mux_pipeline_011_source0_valid;                                                                                   // mux_pipeline_011:out_valid -> rsp_xbar_mux_002:sink0_valid
	wire          mux_pipeline_011_source0_startofpacket;                                                                           // mux_pipeline_011:out_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
	wire  [152:0] mux_pipeline_011_source0_data;                                                                                    // mux_pipeline_011:out_data -> rsp_xbar_mux_002:sink0_data
	wire    [3:0] mux_pipeline_011_source0_channel;                                                                                 // mux_pipeline_011:out_channel -> rsp_xbar_mux_002:sink0_channel
	wire          mux_pipeline_011_source0_ready;                                                                                   // rsp_xbar_mux_002:sink0_ready -> mux_pipeline_011:out_ready
	wire          rsp_xbar_demux_002_src0_endofpacket;                                                                              // rsp_xbar_demux_002:src0_endofpacket -> mux_pipeline_012:in_endofpacket
	wire          rsp_xbar_demux_002_src0_valid;                                                                                    // rsp_xbar_demux_002:src0_valid -> mux_pipeline_012:in_valid
	wire          rsp_xbar_demux_002_src0_startofpacket;                                                                            // rsp_xbar_demux_002:src0_startofpacket -> mux_pipeline_012:in_startofpacket
	wire  [152:0] rsp_xbar_demux_002_src0_data;                                                                                     // rsp_xbar_demux_002:src0_data -> mux_pipeline_012:in_data
	wire    [3:0] rsp_xbar_demux_002_src0_channel;                                                                                  // rsp_xbar_demux_002:src0_channel -> mux_pipeline_012:in_channel
	wire          rsp_xbar_demux_002_src0_ready;                                                                                    // mux_pipeline_012:in_ready -> rsp_xbar_demux_002:src0_ready
	wire          mux_pipeline_012_source0_endofpacket;                                                                             // mux_pipeline_012:out_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
	wire          mux_pipeline_012_source0_valid;                                                                                   // mux_pipeline_012:out_valid -> rsp_xbar_mux_002:sink1_valid
	wire          mux_pipeline_012_source0_startofpacket;                                                                           // mux_pipeline_012:out_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
	wire  [152:0] mux_pipeline_012_source0_data;                                                                                    // mux_pipeline_012:out_data -> rsp_xbar_mux_002:sink1_data
	wire    [3:0] mux_pipeline_012_source0_channel;                                                                                 // mux_pipeline_012:out_channel -> rsp_xbar_mux_002:sink1_channel
	wire          mux_pipeline_012_source0_ready;                                                                                   // rsp_xbar_mux_002:sink1_ready -> mux_pipeline_012:out_ready
	wire          rsp_xbar_demux_003_src0_endofpacket;                                                                              // rsp_xbar_demux_003:src0_endofpacket -> mux_pipeline_013:in_endofpacket
	wire          rsp_xbar_demux_003_src0_valid;                                                                                    // rsp_xbar_demux_003:src0_valid -> mux_pipeline_013:in_valid
	wire          rsp_xbar_demux_003_src0_startofpacket;                                                                            // rsp_xbar_demux_003:src0_startofpacket -> mux_pipeline_013:in_startofpacket
	wire  [152:0] rsp_xbar_demux_003_src0_data;                                                                                     // rsp_xbar_demux_003:src0_data -> mux_pipeline_013:in_data
	wire    [3:0] rsp_xbar_demux_003_src0_channel;                                                                                  // rsp_xbar_demux_003:src0_channel -> mux_pipeline_013:in_channel
	wire          rsp_xbar_demux_003_src0_ready;                                                                                    // mux_pipeline_013:in_ready -> rsp_xbar_demux_003:src0_ready
	wire          mux_pipeline_013_source0_endofpacket;                                                                             // mux_pipeline_013:out_endofpacket -> rsp_xbar_mux_002:sink2_endofpacket
	wire          mux_pipeline_013_source0_valid;                                                                                   // mux_pipeline_013:out_valid -> rsp_xbar_mux_002:sink2_valid
	wire          mux_pipeline_013_source0_startofpacket;                                                                           // mux_pipeline_013:out_startofpacket -> rsp_xbar_mux_002:sink2_startofpacket
	wire  [152:0] mux_pipeline_013_source0_data;                                                                                    // mux_pipeline_013:out_data -> rsp_xbar_mux_002:sink2_data
	wire    [3:0] mux_pipeline_013_source0_channel;                                                                                 // mux_pipeline_013:out_channel -> rsp_xbar_mux_002:sink2_channel
	wire          mux_pipeline_013_source0_ready;                                                                                   // rsp_xbar_mux_002:sink2_ready -> mux_pipeline_013:out_ready
	wire          cmd_xbar_demux_003_src0_endofpacket;                                                                              // cmd_xbar_demux_003:src0_endofpacket -> mux_pipeline_014:in_endofpacket
	wire          cmd_xbar_demux_003_src0_valid;                                                                                    // cmd_xbar_demux_003:src0_valid -> mux_pipeline_014:in_valid
	wire          cmd_xbar_demux_003_src0_startofpacket;                                                                            // cmd_xbar_demux_003:src0_startofpacket -> mux_pipeline_014:in_startofpacket
	wire  [152:0] cmd_xbar_demux_003_src0_data;                                                                                     // cmd_xbar_demux_003:src0_data -> mux_pipeline_014:in_data
	wire    [2:0] cmd_xbar_demux_003_src0_channel;                                                                                  // cmd_xbar_demux_003:src0_channel -> mux_pipeline_014:in_channel
	wire          cmd_xbar_demux_003_src0_ready;                                                                                    // mux_pipeline_014:in_ready -> cmd_xbar_demux_003:src0_ready
	wire          mux_pipeline_014_source0_endofpacket;                                                                             // mux_pipeline_014:out_endofpacket -> width_adapter_004:in_endofpacket
	wire          mux_pipeline_014_source0_valid;                                                                                   // mux_pipeline_014:out_valid -> width_adapter_004:in_valid
	wire          mux_pipeline_014_source0_startofpacket;                                                                           // mux_pipeline_014:out_startofpacket -> width_adapter_004:in_startofpacket
	wire  [152:0] mux_pipeline_014_source0_data;                                                                                    // mux_pipeline_014:out_data -> width_adapter_004:in_data
	wire    [2:0] mux_pipeline_014_source0_channel;                                                                                 // mux_pipeline_014:out_channel -> width_adapter_004:in_channel
	wire          cmd_xbar_demux_003_src1_endofpacket;                                                                              // cmd_xbar_demux_003:src1_endofpacket -> mux_pipeline_015:in_endofpacket
	wire          cmd_xbar_demux_003_src1_valid;                                                                                    // cmd_xbar_demux_003:src1_valid -> mux_pipeline_015:in_valid
	wire          cmd_xbar_demux_003_src1_startofpacket;                                                                            // cmd_xbar_demux_003:src1_startofpacket -> mux_pipeline_015:in_startofpacket
	wire  [152:0] cmd_xbar_demux_003_src1_data;                                                                                     // cmd_xbar_demux_003:src1_data -> mux_pipeline_015:in_data
	wire    [2:0] cmd_xbar_demux_003_src1_channel;                                                                                  // cmd_xbar_demux_003:src1_channel -> mux_pipeline_015:in_channel
	wire          cmd_xbar_demux_003_src1_ready;                                                                                    // mux_pipeline_015:in_ready -> cmd_xbar_demux_003:src1_ready
	wire          mux_pipeline_015_source0_endofpacket;                                                                             // mux_pipeline_015:out_endofpacket -> width_adapter_006:in_endofpacket
	wire          mux_pipeline_015_source0_valid;                                                                                   // mux_pipeline_015:out_valid -> width_adapter_006:in_valid
	wire          mux_pipeline_015_source0_startofpacket;                                                                           // mux_pipeline_015:out_startofpacket -> width_adapter_006:in_startofpacket
	wire  [152:0] mux_pipeline_015_source0_data;                                                                                    // mux_pipeline_015:out_data -> width_adapter_006:in_data
	wire    [2:0] mux_pipeline_015_source0_channel;                                                                                 // mux_pipeline_015:out_channel -> width_adapter_006:in_channel
	wire          cmd_xbar_demux_003_src2_endofpacket;                                                                              // cmd_xbar_demux_003:src2_endofpacket -> mux_pipeline_016:in_endofpacket
	wire          cmd_xbar_demux_003_src2_valid;                                                                                    // cmd_xbar_demux_003:src2_valid -> mux_pipeline_016:in_valid
	wire          cmd_xbar_demux_003_src2_startofpacket;                                                                            // cmd_xbar_demux_003:src2_startofpacket -> mux_pipeline_016:in_startofpacket
	wire  [152:0] cmd_xbar_demux_003_src2_data;                                                                                     // cmd_xbar_demux_003:src2_data -> mux_pipeline_016:in_data
	wire    [2:0] cmd_xbar_demux_003_src2_channel;                                                                                  // cmd_xbar_demux_003:src2_channel -> mux_pipeline_016:in_channel
	wire          cmd_xbar_demux_003_src2_ready;                                                                                    // mux_pipeline_016:in_ready -> cmd_xbar_demux_003:src2_ready
	wire          mux_pipeline_016_source0_endofpacket;                                                                             // mux_pipeline_016:out_endofpacket -> width_adapter_008:in_endofpacket
	wire          mux_pipeline_016_source0_valid;                                                                                   // mux_pipeline_016:out_valid -> width_adapter_008:in_valid
	wire          mux_pipeline_016_source0_startofpacket;                                                                           // mux_pipeline_016:out_startofpacket -> width_adapter_008:in_startofpacket
	wire  [152:0] mux_pipeline_016_source0_data;                                                                                    // mux_pipeline_016:out_data -> width_adapter_008:in_data
	wire    [2:0] mux_pipeline_016_source0_channel;                                                                                 // mux_pipeline_016:out_channel -> width_adapter_008:in_channel
	wire          rsp_xbar_demux_004_src0_endofpacket;                                                                              // rsp_xbar_demux_004:src0_endofpacket -> mux_pipeline_017:in_endofpacket
	wire          rsp_xbar_demux_004_src0_valid;                                                                                    // rsp_xbar_demux_004:src0_valid -> mux_pipeline_017:in_valid
	wire          rsp_xbar_demux_004_src0_startofpacket;                                                                            // rsp_xbar_demux_004:src0_startofpacket -> mux_pipeline_017:in_startofpacket
	wire  [152:0] rsp_xbar_demux_004_src0_data;                                                                                     // rsp_xbar_demux_004:src0_data -> mux_pipeline_017:in_data
	wire    [2:0] rsp_xbar_demux_004_src0_channel;                                                                                  // rsp_xbar_demux_004:src0_channel -> mux_pipeline_017:in_channel
	wire          rsp_xbar_demux_004_src0_ready;                                                                                    // mux_pipeline_017:in_ready -> rsp_xbar_demux_004:src0_ready
	wire          mux_pipeline_017_source0_endofpacket;                                                                             // mux_pipeline_017:out_endofpacket -> rsp_xbar_mux_003:sink0_endofpacket
	wire          mux_pipeline_017_source0_valid;                                                                                   // mux_pipeline_017:out_valid -> rsp_xbar_mux_003:sink0_valid
	wire          mux_pipeline_017_source0_startofpacket;                                                                           // mux_pipeline_017:out_startofpacket -> rsp_xbar_mux_003:sink0_startofpacket
	wire  [152:0] mux_pipeline_017_source0_data;                                                                                    // mux_pipeline_017:out_data -> rsp_xbar_mux_003:sink0_data
	wire    [2:0] mux_pipeline_017_source0_channel;                                                                                 // mux_pipeline_017:out_channel -> rsp_xbar_mux_003:sink0_channel
	wire          mux_pipeline_017_source0_ready;                                                                                   // rsp_xbar_mux_003:sink0_ready -> mux_pipeline_017:out_ready
	wire          rsp_xbar_demux_005_src0_endofpacket;                                                                              // rsp_xbar_demux_005:src0_endofpacket -> mux_pipeline_018:in_endofpacket
	wire          rsp_xbar_demux_005_src0_valid;                                                                                    // rsp_xbar_demux_005:src0_valid -> mux_pipeline_018:in_valid
	wire          rsp_xbar_demux_005_src0_startofpacket;                                                                            // rsp_xbar_demux_005:src0_startofpacket -> mux_pipeline_018:in_startofpacket
	wire  [152:0] rsp_xbar_demux_005_src0_data;                                                                                     // rsp_xbar_demux_005:src0_data -> mux_pipeline_018:in_data
	wire    [2:0] rsp_xbar_demux_005_src0_channel;                                                                                  // rsp_xbar_demux_005:src0_channel -> mux_pipeline_018:in_channel
	wire          rsp_xbar_demux_005_src0_ready;                                                                                    // mux_pipeline_018:in_ready -> rsp_xbar_demux_005:src0_ready
	wire          mux_pipeline_018_source0_endofpacket;                                                                             // mux_pipeline_018:out_endofpacket -> rsp_xbar_mux_003:sink1_endofpacket
	wire          mux_pipeline_018_source0_valid;                                                                                   // mux_pipeline_018:out_valid -> rsp_xbar_mux_003:sink1_valid
	wire          mux_pipeline_018_source0_startofpacket;                                                                           // mux_pipeline_018:out_startofpacket -> rsp_xbar_mux_003:sink1_startofpacket
	wire  [152:0] mux_pipeline_018_source0_data;                                                                                    // mux_pipeline_018:out_data -> rsp_xbar_mux_003:sink1_data
	wire    [2:0] mux_pipeline_018_source0_channel;                                                                                 // mux_pipeline_018:out_channel -> rsp_xbar_mux_003:sink1_channel
	wire          mux_pipeline_018_source0_ready;                                                                                   // rsp_xbar_mux_003:sink1_ready -> mux_pipeline_018:out_ready
	wire          rsp_xbar_demux_006_src0_endofpacket;                                                                              // rsp_xbar_demux_006:src0_endofpacket -> mux_pipeline_019:in_endofpacket
	wire          rsp_xbar_demux_006_src0_valid;                                                                                    // rsp_xbar_demux_006:src0_valid -> mux_pipeline_019:in_valid
	wire          rsp_xbar_demux_006_src0_startofpacket;                                                                            // rsp_xbar_demux_006:src0_startofpacket -> mux_pipeline_019:in_startofpacket
	wire  [152:0] rsp_xbar_demux_006_src0_data;                                                                                     // rsp_xbar_demux_006:src0_data -> mux_pipeline_019:in_data
	wire    [2:0] rsp_xbar_demux_006_src0_channel;                                                                                  // rsp_xbar_demux_006:src0_channel -> mux_pipeline_019:in_channel
	wire          rsp_xbar_demux_006_src0_ready;                                                                                    // mux_pipeline_019:in_ready -> rsp_xbar_demux_006:src0_ready
	wire          mux_pipeline_019_source0_endofpacket;                                                                             // mux_pipeline_019:out_endofpacket -> rsp_xbar_mux_003:sink2_endofpacket
	wire          mux_pipeline_019_source0_valid;                                                                                   // mux_pipeline_019:out_valid -> rsp_xbar_mux_003:sink2_valid
	wire          mux_pipeline_019_source0_startofpacket;                                                                           // mux_pipeline_019:out_startofpacket -> rsp_xbar_mux_003:sink2_startofpacket
	wire  [152:0] mux_pipeline_019_source0_data;                                                                                    // mux_pipeline_019:out_data -> rsp_xbar_mux_003:sink2_data
	wire    [2:0] mux_pipeline_019_source0_channel;                                                                                 // mux_pipeline_019:out_channel -> rsp_xbar_mux_003:sink2_channel
	wire          mux_pipeline_019_source0_ready;                                                                                   // rsp_xbar_mux_003:sink2_ready -> mux_pipeline_019:out_ready
	wire          irq_mapper_receiver0_irq;                                                                                         // modular_sgdma_dispatcher_0:csr_irq -> irq_mapper:receiver0_irq
	wire   [15:0] pcie_hard_ip_0_rxm_irq_irq;                                                                                       // irq_synchronizer:sender_irq -> pcie_hard_ip_0:rxm_irq_irq
	wire   [15:0] irq_synchronizer_receiver_irq;                                                                                    // irq_mapper:sender_irq -> irq_synchronizer:receiver_irq

	q_sys_pcie_hard_ip_0 #(
		.p_pcie_hip_type                     ("2"),
		.lane_mask                           (8'b11111110),
		.max_link_width                      (1),
		.millisecond_cycle_count             ("125000"),
		.enable_gen2_core                    ("false"),
		.gen2_lane_rate_mode                 ("false"),
		.no_soft_reset                       ("false"),
		.core_clk_divider                    (2),
		.enable_ch0_pclk_out                 ("true"),
		.core_clk_source                     ("pclk"),
		.CB_P2A_AVALON_ADDR_B0               (0),
		.bar0_size_mask                      (27),
		.bar0_io_space                       ("false"),
		.bar0_64bit_mem_space                ("true"),
		.bar0_prefetchable                   ("true"),
		.CB_P2A_AVALON_ADDR_B1               (0),
		.bar1_size_mask                      (0),
		.bar1_io_space                       ("false"),
		.bar1_64bit_mem_space                ("true"),
		.bar1_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B2               (0),
		.bar2_size_mask                      (27),
		.bar2_io_space                       ("false"),
		.bar2_64bit_mem_space                ("false"),
		.bar2_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B3               (0),
		.bar3_size_mask                      (0),
		.bar3_io_space                       ("false"),
		.bar3_64bit_mem_space                ("false"),
		.bar3_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B4               (0),
		.bar4_size_mask                      (0),
		.bar4_io_space                       ("false"),
		.bar4_64bit_mem_space                ("false"),
		.bar4_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B5               (0),
		.bar5_size_mask                      (0),
		.bar5_io_space                       ("false"),
		.bar5_64bit_mem_space                ("false"),
		.bar5_prefetchable                   ("false"),
		.vendor_id                           (4466),
		.device_id                           (57345),
		.revision_id                         (9),
		.class_code                          (16711680),
		.subsystem_vendor_id                 (4466),
		.subsystem_device_id                 (4420),
		.port_link_number                    (1),
		.msi_function_count                  (0),
		.enable_msi_64bit_addressing         ("true"),
		.enable_function_msix_support        ("false"),
		.eie_before_nfts_count               (4),
		.enable_completion_timeout_disable   ("false"),
		.completion_timeout                  ("NONE"),
		.enable_adapter_half_rate_mode       ("false"),
		.msix_pba_bir                        (0),
		.msix_pba_offset                     (0),
		.msix_table_bir                      (0),
		.msix_table_offset                   (0),
		.msix_table_size                     (0),
		.use_crc_forwarding                  ("false"),
		.surprise_down_error_support         ("false"),
		.dll_active_report_support           ("false"),
		.bar_io_window_size                  ("32BIT"),
		.bar_prefetchable                    (32),
		.hot_plug_support                    (7'b0000000),
		.no_command_completed                ("true"),
		.slot_power_limit                    (0),
		.slot_power_scale                    (0),
		.slot_number                         (0),
		.enable_slot_register                ("false"),
		.advanced_errors                     ("false"),
		.enable_ecrc_check                   ("false"),
		.enable_ecrc_gen                     ("false"),
		.max_payload_size                    (1),
		.retry_buffer_last_active_address    (255),
		.credit_buffer_allocation_aux        ("ABSOLUTE"),
		.vc0_rx_flow_ctrl_posted_header      (13),
		.vc0_rx_flow_ctrl_posted_data        (107),
		.vc0_rx_flow_ctrl_nonposted_header   (8),
		.vc0_rx_flow_ctrl_nonposted_data     (0),
		.vc0_rx_flow_ctrl_compl_header       (48),
		.vc0_rx_flow_ctrl_compl_data         (256),
		.RX_BUF                              (9),
		.RH_NUM                              (7),
		.G_TAG_NUM0                          (32),
		.endpoint_l0_latency                 (0),
		.endpoint_l1_latency                 (0),
		.enable_l1_aspm                      ("false"),
		.l01_entry_latency                   (31),
		.diffclock_nfts_count                (255),
		.sameclock_nfts_count                (255),
		.l1_exit_latency_sameclock           (7),
		.l1_exit_latency_diffclock           (7),
		.l0_exit_latency_sameclock           (7),
		.l0_exit_latency_diffclock           (7),
		.gen2_diffclock_nfts_count           (255),
		.gen2_sameclock_nfts_count           (255),
		.CG_COMMON_CLOCK_MODE                (1),
		.CB_PCIE_MODE                        (0),
		.AST_LITE                            (0),
		.CB_PCIE_RX_LITE                     (0),
		.CG_RXM_IRQ_NUM                      (16),
		.CG_AVALON_S_ADDR_WIDTH              (20),
		.bypass_tl                           ("false"),
		.CG_IMPL_CRA_AV_SLAVE_PORT           (1),
		.CG_NO_CPL_REORDERING                (0),
		.CG_ENABLE_A2P_INTERRUPT             (0),
		.CG_IRQ_BIT_ENA                      (65535),
		.CB_A2P_ADDR_MAP_IS_FIXED            (0),
		.CB_A2P_ADDR_MAP_NUM_ENTRIES         (2),
		.CB_A2P_ADDR_MAP_PASS_THRU_BITS      (19),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW  (32'b00000000000000000000000000000000),
		.RXM_DATA_WIDTH                      (64),
		.RXM_BEN_WIDTH                       (8),
		.TL_SELECTION                        (1),
		.pcie_mode                           ("SHARED_MODE"),
		.single_rx_detect                    (1),
		.enable_coreclk_out_half_rate        ("false"),
		.low_priority_vc                     (0),
		.link_width                          (1),
		.cyclone4                            (1)
	) pcie_hard_ip_0 (
		.pcie_core_clk_clk                  (pcie_hard_ip_0_pcie_core_clk_clk),                                //      pcie_core_clk.clk
		.pcie_core_reset_reset_n            (pcie_hard_ip_0_pcie_core_reset_reset),                            //    pcie_core_reset.reset_n
		.cal_blk_clk_clk                    (clk_clk),                                                         //        cal_blk_clk.clk
		.txs_address                        (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_address),       //                txs.address
		.txs_chipselect                     (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_chipselect),    //                   .chipselect
		.txs_byteenable                     (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_byteenable),    //                   .byteenable
		.txs_readdata                       (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdata),      //                   .readdata
		.txs_writedata                      (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_writedata),     //                   .writedata
		.txs_read                           (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_read),          //                   .read
		.txs_write                          (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_write),         //                   .write
		.txs_burstcount                     (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_burstcount),    //                   .burstcount
		.txs_readdatavalid                  (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdatavalid), //                   .readdatavalid
		.txs_waitrequest                    (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_waitrequest),   //                   .waitrequest
		.refclk_export                      (pcie_hard_ip_0_refclk_export),                                    //             refclk.export
		.test_in_test_in                    (pcie_hard_ip_0_test_in_test_in),                                  //            test_in.test_in
		.pcie_rstn_export                   (pcie_hard_ip_0_pcie_rstn_export),                                 //          pcie_rstn.export
		.clocks_sim_clk250_export           (pcie_hard_ip_0_clocks_sim_clk250_export),                         //         clocks_sim.clk250_export
		.clocks_sim_clk500_export           (pcie_hard_ip_0_clocks_sim_clk500_export),                         //                   .clk500_export
		.clocks_sim_clk125_export           (pcie_hard_ip_0_clocks_sim_clk125_export),                         //                   .clk125_export
		.reconfig_busy_busy_altgxb_reconfig (pcie_hard_ip_0_reconfig_busy_busy_altgxb_reconfig),               //      reconfig_busy.busy_altgxb_reconfig
		.pipe_ext_pipe_mode                 (pcie_hard_ip_0_pipe_ext_pipe_mode),                               //           pipe_ext.pipe_mode
		.pipe_ext_phystatus_ext             (pcie_hard_ip_0_pipe_ext_phystatus_ext),                           //                   .phystatus_ext
		.pipe_ext_rate_ext                  (pcie_hard_ip_0_pipe_ext_rate_ext),                                //                   .rate_ext
		.pipe_ext_powerdown_ext             (pcie_hard_ip_0_pipe_ext_powerdown_ext),                           //                   .powerdown_ext
		.pipe_ext_txdetectrx_ext            (pcie_hard_ip_0_pipe_ext_txdetectrx_ext),                          //                   .txdetectrx_ext
		.pipe_ext_rxelecidle0_ext           (pcie_hard_ip_0_pipe_ext_rxelecidle0_ext),                         //                   .rxelecidle0_ext
		.pipe_ext_rxdata0_ext               (pcie_hard_ip_0_pipe_ext_rxdata0_ext),                             //                   .rxdata0_ext
		.pipe_ext_rxstatus0_ext             (pcie_hard_ip_0_pipe_ext_rxstatus0_ext),                           //                   .rxstatus0_ext
		.pipe_ext_rxvalid0_ext              (pcie_hard_ip_0_pipe_ext_rxvalid0_ext),                            //                   .rxvalid0_ext
		.pipe_ext_rxdatak0_ext              (pcie_hard_ip_0_pipe_ext_rxdatak0_ext),                            //                   .rxdatak0_ext
		.pipe_ext_txdata0_ext               (pcie_hard_ip_0_pipe_ext_txdata0_ext),                             //                   .txdata0_ext
		.pipe_ext_txdatak0_ext              (pcie_hard_ip_0_pipe_ext_txdatak0_ext),                            //                   .txdatak0_ext
		.pipe_ext_rxpolarity0_ext           (pcie_hard_ip_0_pipe_ext_rxpolarity0_ext),                         //                   .rxpolarity0_ext
		.pipe_ext_txcompl0_ext              (pcie_hard_ip_0_pipe_ext_txcompl0_ext),                            //                   .txcompl0_ext
		.pipe_ext_txelecidle0_ext           (pcie_hard_ip_0_pipe_ext_txelecidle0_ext),                         //                   .txelecidle0_ext
		.powerdown_pll_powerdown            (),                                                                //          powerdown.pll_powerdown
		.powerdown_gxb_powerdown            (),                                                                //                   .gxb_powerdown
		.test_out_test_out                  (pcie_hard_ip_0_test_out_test_out),                                //           test_out.test_out
		.bar1_0_address                     (pcie_hard_ip_0_bar1_0_address),                                   //             bar1_0.address
		.bar1_0_read                        (pcie_hard_ip_0_bar1_0_read),                                      //                   .read
		.bar1_0_waitrequest                 (pcie_hard_ip_0_bar1_0_waitrequest),                               //                   .waitrequest
		.bar1_0_write                       (pcie_hard_ip_0_bar1_0_write),                                     //                   .write
		.bar1_0_readdatavalid               (pcie_hard_ip_0_bar1_0_readdatavalid),                             //                   .readdatavalid
		.bar1_0_readdata                    (pcie_hard_ip_0_bar1_0_readdata),                                  //                   .readdata
		.bar1_0_writedata                   (pcie_hard_ip_0_bar1_0_writedata),                                 //                   .writedata
		.bar1_0_burstcount                  (pcie_hard_ip_0_bar1_0_burstcount),                                //                   .burstcount
		.bar1_0_byteenable                  (pcie_hard_ip_0_bar1_0_byteenable),                                //                   .byteenable
		.bar2_address                       (pcie_hard_ip_0_bar2_address),                                     //               bar2.address
		.bar2_read                          (pcie_hard_ip_0_bar2_read),                                        //                   .read
		.bar2_waitrequest                   (pcie_hard_ip_0_bar2_waitrequest),                                 //                   .waitrequest
		.bar2_write                         (pcie_hard_ip_0_bar2_write),                                       //                   .write
		.bar2_readdatavalid                 (pcie_hard_ip_0_bar2_readdatavalid),                               //                   .readdatavalid
		.bar2_readdata                      (pcie_hard_ip_0_bar2_readdata),                                    //                   .readdata
		.bar2_writedata                     (pcie_hard_ip_0_bar2_writedata),                                   //                   .writedata
		.bar2_burstcount                    (pcie_hard_ip_0_bar2_burstcount),                                  //                   .burstcount
		.bar2_byteenable                    (pcie_hard_ip_0_bar2_byteenable),                                  //                   .byteenable
		.cra_chipselect                     (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_chipselect),    //                cra.chipselect
		.cra_address                        (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_address),       //                   .address
		.cra_byteenable                     (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_byteenable),    //                   .byteenable
		.cra_read                           (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_read),          //                   .read
		.cra_readdata                       (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_readdata),      //                   .readdata
		.cra_write                          (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_write),         //                   .write
		.cra_writedata                      (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_writedata),     //                   .writedata
		.cra_waitrequest                    (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_waitrequest),   //                   .waitrequest
		.cra_irq_irq                        (),                                                                //            cra_irq.irq
		.rxm_irq_irq                        (pcie_hard_ip_0_rxm_irq_irq),                                      //            rxm_irq.irq
		.rx_in_rx_datain_0                  (pcie_hard_ip_0_rx_in_rx_datain_0),                                //              rx_in.rx_datain_0
		.tx_out_tx_dataout_0                (pcie_hard_ip_0_tx_out_tx_dataout_0),                              //             tx_out.tx_dataout_0
		.reconfig_togxb_data                (pcie_hard_ip_0_reconfig_togxb_data),                              //     reconfig_togxb.data
		.reconfig_gxbclk_clk                (clk_clk),                                                         //    reconfig_gxbclk.clk
		.reconfig_fromgxb_0_data            (pcie_hard_ip_0_reconfig_fromgxb_0_data),                          // reconfig_fromgxb_0.data
		.fixedclk_clk                       (pcie_hard_ip_0_fixedclk_clk)                                      //           fixedclk.clk
	);

	q_sys_onchip_memory2_0 onchip_memory2_0 (
		.clk        (pcie_hard_ip_0_pcie_core_clk_clk),                              //   clk1.clk
		.address    (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address),    //     s1.address
		.chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), //       .chipselect
		.clken      (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken),      //       .clken
		.readdata   (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata),   //       .readdata
		.write      (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write),      //       .write
		.writedata  (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata),  //       .writedata
		.byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset)                                 // reset1.reset
	);

	dispatcher #(
		.MODE                        (0),
		.RESPONSE_PORT               (2),
		.DESCRIPTOR_FIFO_DEPTH       (8),
		.ENHANCED_FEATURES           (0),
		.DESCRIPTOR_WIDTH            (128),
		.DESCRIPTOR_BYTEENABLE_WIDTH (16),
		.CSR_ADDRESS_WIDTH           (3)
	) modular_sgdma_dispatcher_0 (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                       //                clock.clk
		.reset                   (rst_controller_reset_out_reset),                                                         //          clock_reset.reset
		.csr_writedata           (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_writedata),                //                  CSR.writedata
		.csr_write               (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_write),                    //                     .write
		.csr_byteenable          (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_byteenable),               //                     .byteenable
		.csr_readdata            (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_readdata),                 //                     .readdata
		.csr_read                (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_read),                     //                     .read
		.csr_address             (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_address),                  //                     .address
		.descriptor_write        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_write),       //     Descriptor_Slave.write
		.descriptor_waitrequest  (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_waitrequest), //                     .waitrequest
		.descriptor_writedata    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_writedata),   //                     .writedata
		.descriptor_byteenable   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_byteenable),  //                     .byteenable
		.src_write_master_data   (modular_sgdma_dispatcher_0_write_command_source_data),                                   // Write_Command_Source.data
		.src_write_master_valid  (modular_sgdma_dispatcher_0_write_command_source_valid),                                  //                     .valid
		.src_write_master_ready  (modular_sgdma_dispatcher_0_write_command_source_ready),                                  //                     .ready
		.snk_write_master_data   (dma_write_master_0_response_source_data),                                                //  Write_Response_Sink.data
		.snk_write_master_valid  (dma_write_master_0_response_source_valid),                                               //                     .valid
		.snk_write_master_ready  (dma_write_master_0_response_source_ready),                                               //                     .ready
		.src_read_master_data    (modular_sgdma_dispatcher_0_read_command_source_data),                                    //  Read_Command_Source.data
		.src_read_master_valid   (modular_sgdma_dispatcher_0_read_command_source_valid),                                   //                     .valid
		.src_read_master_ready   (modular_sgdma_dispatcher_0_read_command_source_ready),                                   //                     .ready
		.snk_read_master_data    (dma_read_master_0_response_source_data),                                                 //   Read_Response_Sink.data
		.snk_read_master_valid   (dma_read_master_0_response_source_valid),                                                //                     .valid
		.snk_read_master_ready   (dma_read_master_0_response_source_ready),                                                //                     .ready
		.csr_irq                 (irq_mapper_receiver0_irq),                                                               //              csr_irq.irq
		.src_response_data       (),                                                                                       //          (terminated)
		.src_response_valid      (),                                                                                       //          (terminated)
		.src_response_ready      (1'b0),                                                                                   //          (terminated)
		.mm_response_waitrequest (),                                                                                       //          (terminated)
		.mm_response_byteenable  (4'b0000),                                                                                //          (terminated)
		.mm_response_address     (1'b0),                                                                                   //          (terminated)
		.mm_response_readdata    (),                                                                                       //          (terminated)
		.mm_response_read        (1'b0)                                                                                    //          (terminated)
	);

	read_master #(
		.DATA_WIDTH                (64),
		.LENGTH_WIDTH              (15),
		.FIFO_DEPTH                (64),
		.STRIDE_ENABLE             (0),
		.BURST_ENABLE              (1),
		.PACKET_ENABLE             (0),
		.ERROR_ENABLE              (0),
		.ERROR_WIDTH               (8),
		.CHANNEL_ENABLE            (0),
		.CHANNEL_WIDTH             (8),
		.BYTE_ENABLE_WIDTH         (8),
		.BYTE_ENABLE_WIDTH_LOG2    (3),
		.ADDRESS_WIDTH             (27),
		.FIFO_DEPTH_LOG2           (6),
		.SYMBOL_WIDTH              (8),
		.NUMBER_OF_SYMBOLS         (8),
		.NUMBER_OF_SYMBOLS_LOG2    (3),
		.MAX_BURST_COUNT_WIDTH     (5),
		.UNALIGNED_ACCESSES_ENABLE (0),
		.ONLY_FULL_ACCESS_ENABLE   (1),
		.BURST_WRAPPING_SUPPORT    (0),
		.PROGRAMMABLE_BURST_ENABLE (0),
		.MAX_BURST_COUNT           (16),
		.FIFO_SPEED_OPTIMIZATION   (1),
		.STRIDE_WIDTH              (1)
	) dma_read_master_0 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),                     //            Clock.clk
		.reset                (rst_controller_reset_out_reset),                       //      Clock_reset.reset
		.master_address       (dma_read_master_0_data_read_master_address),           // Data_Read_Master.address
		.master_read          (dma_read_master_0_data_read_master_read),              //                 .read
		.master_byteenable    (dma_read_master_0_data_read_master_byteenable),        //                 .byteenable
		.master_readdata      (dma_read_master_0_data_read_master_readdata),          //                 .readdata
		.master_waitrequest   (dma_read_master_0_data_read_master_waitrequest),       //                 .waitrequest
		.master_readdatavalid (dma_read_master_0_data_read_master_readdatavalid),     //                 .readdatavalid
		.master_burstcount    (dma_read_master_0_data_read_master_burstcount),        //                 .burstcount
		.src_data             (dma_read_master_0_data_source_data),                   //      Data_Source.data
		.src_valid            (dma_read_master_0_data_source_valid),                  //                 .valid
		.src_ready            (dma_read_master_0_data_source_ready),                  //                 .ready
		.snk_command_data     (modular_sgdma_dispatcher_0_read_command_source_data),  //     Command_Sink.data
		.snk_command_valid    (modular_sgdma_dispatcher_0_read_command_source_valid), //                 .valid
		.snk_command_ready    (modular_sgdma_dispatcher_0_read_command_source_ready), //                 .ready
		.src_response_data    (dma_read_master_0_response_source_data),               //  Response_Source.data
		.src_response_valid   (dma_read_master_0_response_source_valid),              //                 .valid
		.src_response_ready   (dma_read_master_0_response_source_ready),              //                 .ready
		.src_sop              (),                                                     //      (terminated)
		.src_eop              (),                                                     //      (terminated)
		.src_empty            (),                                                     //      (terminated)
		.src_error            (),                                                     //      (terminated)
		.src_channel          ()                                                      //      (terminated)
	);

	write_master #(
		.DATA_WIDTH                     (64),
		.LENGTH_WIDTH                   (15),
		.FIFO_DEPTH                     (64),
		.STRIDE_ENABLE                  (0),
		.BURST_ENABLE                   (1),
		.PACKET_ENABLE                  (0),
		.ERROR_ENABLE                   (0),
		.ERROR_WIDTH                    (8),
		.BYTE_ENABLE_WIDTH              (8),
		.BYTE_ENABLE_WIDTH_LOG2         (3),
		.ADDRESS_WIDTH                  (27),
		.FIFO_DEPTH_LOG2                (6),
		.SYMBOL_WIDTH                   (8),
		.NUMBER_OF_SYMBOLS              (8),
		.NUMBER_OF_SYMBOLS_LOG2         (3),
		.MAX_BURST_COUNT_WIDTH          (5),
		.UNALIGNED_ACCESSES_ENABLE      (0),
		.ONLY_FULL_ACCESS_ENABLE        (1),
		.BURST_WRAPPING_SUPPORT         (0),
		.PROGRAMMABLE_BURST_ENABLE      (0),
		.MAX_BURST_COUNT                (16),
		.FIFO_SPEED_OPTIMIZATION        (1),
		.STRIDE_WIDTH                   (1),
		.ACTUAL_BYTES_TRANSFERRED_WIDTH (32)
	) dma_write_master_0 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),                      //             Clock.clk
		.reset              (rst_controller_reset_out_reset),                        //       Clock_reset.reset
		.master_address     (dma_write_master_0_data_write_master_address),          // Data_Write_Master.address
		.master_write       (dma_write_master_0_data_write_master_write),            //                  .write
		.master_byteenable  (dma_write_master_0_data_write_master_byteenable),       //                  .byteenable
		.master_writedata   (dma_write_master_0_data_write_master_writedata),        //                  .writedata
		.master_waitrequest (dma_write_master_0_data_write_master_waitrequest),      //                  .waitrequest
		.master_burstcount  (dma_write_master_0_data_write_master_burstcount),       //                  .burstcount
		.snk_data           (dma_read_master_0_data_source_data),                    //         Data_Sink.data
		.snk_valid          (dma_read_master_0_data_source_valid),                   //                  .valid
		.snk_ready          (dma_read_master_0_data_source_ready),                   //                  .ready
		.snk_command_data   (modular_sgdma_dispatcher_0_write_command_source_data),  //      Command_Sink.data
		.snk_command_valid  (modular_sgdma_dispatcher_0_write_command_source_valid), //                  .valid
		.snk_command_ready  (modular_sgdma_dispatcher_0_write_command_source_ready), //                  .ready
		.src_response_data  (dma_write_master_0_response_source_data),               //   Response_Source.data
		.src_response_valid (dma_write_master_0_response_source_valid),              //                  .valid
		.src_response_ready (dma_write_master_0_response_source_ready),              //                  .ready
		.snk_sop            (1'b0),                                                  //       (terminated)
		.snk_eop            (1'b0),                                                  //       (terminated)
		.snk_empty          (3'b000),                                                //       (terminated)
		.snk_error          (8'b00000000)                                            //       (terminated)
	);

	q_sys_pio_led pio_led (
		.clk        (pcie_hard_ip_0_pcie_core_clk_clk),                     //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),                      //               reset.reset_n
		.address    (pio_led_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~pio_led_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (pio_led_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (pio_led_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (pio_led_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (pio_led_out_export)                                    // external_connection.export
	);

	q_sys_pio_pb pio_pb (
		.clk      (pcie_hard_ip_0_pcie_core_clk_clk),                  //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                   //               reset.reset_n
		.address  (pio_pb_s1_translator_avalon_anti_slave_0_address),  //                  s1.address
		.readdata (pio_pb_s1_translator_avalon_anti_slave_0_readdata), //                    .readdata
		.in_port  (pio_pb_in_export)                                   // external_connection.export
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (27),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (8),
		.USE_READ                    (0),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) dma_write_master_0_data_write_master_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                                        //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                          //                     reset.reset
		.uav_address           (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (dma_write_master_0_data_write_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (dma_write_master_0_data_write_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (dma_write_master_0_data_write_master_burstcount),                                         //                          .burstcount
		.av_byteenable         (dma_write_master_0_data_write_master_byteenable),                                         //                          .byteenable
		.av_write              (dma_write_master_0_data_write_master_write),                                              //                          .write
		.av_writedata          (dma_write_master_0_data_write_master_writedata),                                          //                          .writedata
		.av_beginbursttransfer (1'b0),                                                                                    //               (terminated)
		.av_begintransfer      (1'b0),                                                                                    //               (terminated)
		.av_chipselect         (1'b0),                                                                                    //               (terminated)
		.av_read               (1'b0),                                                                                    //               (terminated)
		.av_readdata           (),                                                                                        //               (terminated)
		.av_readdatavalid      (),                                                                                        //               (terminated)
		.av_lock               (1'b0),                                                                                    //               (terminated)
		.av_debugaccess        (1'b0),                                                                                    //               (terminated)
		.uav_clken             (),                                                                                        //               (terminated)
		.av_clken              (1'b1)                                                                                     //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (27),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (8),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) dma_read_master_0_data_read_master_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                                      //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                        //                     reset.reset
		.uav_address           (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (dma_read_master_0_data_read_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (dma_read_master_0_data_read_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (dma_read_master_0_data_read_master_burstcount),                                         //                          .burstcount
		.av_byteenable         (dma_read_master_0_data_read_master_byteenable),                                         //                          .byteenable
		.av_read               (dma_read_master_0_data_read_master_read),                                               //                          .read
		.av_readdata           (dma_read_master_0_data_read_master_readdata),                                           //                          .readdata
		.av_readdatavalid      (dma_read_master_0_data_read_master_readdatavalid),                                      //                          .readdatavalid
		.av_beginbursttransfer (1'b0),                                                                                  //               (terminated)
		.av_begintransfer      (1'b0),                                                                                  //               (terminated)
		.av_chipselect         (1'b0),                                                                                  //               (terminated)
		.av_write              (1'b0),                                                                                  //               (terminated)
		.av_writedata          (64'b0000000000000000000000000000000000000000000000000000000000000000),                  //               (terminated)
		.av_lock               (1'b0),                                                                                  //               (terminated)
		.av_debugaccess        (1'b0),                                                                                  //               (terminated)
		.uav_clken             (),                                                                                      //               (terminated)
		.av_clken              (1'b1)                                                                                   //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pcie_hard_ip_0_bar1_0_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                         //                       clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                       //                     reset.reset
		.uav_address           (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (pcie_hard_ip_0_bar1_0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (pcie_hard_ip_0_bar1_0_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (pcie_hard_ip_0_bar1_0_burstcount),                                         //                          .burstcount
		.av_byteenable         (pcie_hard_ip_0_bar1_0_byteenable),                                         //                          .byteenable
		.av_read               (pcie_hard_ip_0_bar1_0_read),                                               //                          .read
		.av_readdata           (pcie_hard_ip_0_bar1_0_readdata),                                           //                          .readdata
		.av_readdatavalid      (pcie_hard_ip_0_bar1_0_readdatavalid),                                      //                          .readdatavalid
		.av_write              (pcie_hard_ip_0_bar1_0_write),                                              //                          .write
		.av_writedata          (pcie_hard_ip_0_bar1_0_writedata),                                          //                          .writedata
		.av_beginbursttransfer (1'b0),                                                                     //               (terminated)
		.av_begintransfer      (1'b0),                                                                     //               (terminated)
		.av_chipselect         (1'b0),                                                                     //               (terminated)
		.av_lock               (1'b0),                                                                     //               (terminated)
		.av_debugaccess        (1'b0),                                                                     //               (terminated)
		.uav_clken             (),                                                                         //               (terminated)
		.av_clken              (1'b1)                                                                      //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (4),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_memory2_0_s1_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                               //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                 //                    reset.reset
		.uav_address           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_chipselect         (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_clken              (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken),                       //                         .clken
		.av_read               (),                                                                               //              (terminated)
		.av_begintransfer      (),                                                                               //              (terminated)
		.av_beginbursttransfer (),                                                                               //              (terminated)
		.av_burstcount         (),                                                                               //              (terminated)
		.av_readdatavalid      (1'b0),                                                                           //              (terminated)
		.av_waitrequest        (1'b0),                                                                           //              (terminated)
		.av_writebyteenable    (),                                                                               //              (terminated)
		.av_lock               (),                                                                               //              (terminated)
		.uav_clken             (1'b0),                                                                           //              (terminated)
		.av_debugaccess        (),                                                                               //              (terminated)
		.av_outputenable       ()                                                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (20),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pcie_hard_ip_0_txs_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                              //                      clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                            //                    reset.reset
		.uav_address           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_burstcount         (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_burstcount),                  //                         .burstcount
		.av_byteenable         (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_readdatavalid      (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_readdatavalid),               //                         .readdatavalid
		.av_waitrequest        (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_chipselect         (pcie_hard_ip_0_txs_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pio_led_s1_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                      //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                        //                    reset.reset
		.uav_address           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pio_led_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pio_led_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (pio_led_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pio_led_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (pio_led_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                      //              (terminated)
		.av_begintransfer      (),                                                                      //              (terminated)
		.av_beginbursttransfer (),                                                                      //              (terminated)
		.av_burstcount         (),                                                                      //              (terminated)
		.av_byteenable         (),                                                                      //              (terminated)
		.av_readdatavalid      (1'b0),                                                                  //              (terminated)
		.av_waitrequest        (1'b0),                                                                  //              (terminated)
		.av_writebyteenable    (),                                                                      //              (terminated)
		.av_lock               (),                                                                      //              (terminated)
		.av_clken              (),                                                                      //              (terminated)
		.uav_clken             (1'b0),                                                                  //              (terminated)
		.av_debugaccess        (),                                                                      //              (terminated)
		.av_outputenable       ()                                                                       //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pio_pb_s1_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                     //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                       //                    reset.reset
		.uav_address           (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pio_pb_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_readdata           (pio_pb_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_write              (),                                                                     //              (terminated)
		.av_read               (),                                                                     //              (terminated)
		.av_writedata          (),                                                                     //              (terminated)
		.av_begintransfer      (),                                                                     //              (terminated)
		.av_beginbursttransfer (),                                                                     //              (terminated)
		.av_burstcount         (),                                                                     //              (terminated)
		.av_byteenable         (),                                                                     //              (terminated)
		.av_readdatavalid      (1'b0),                                                                 //              (terminated)
		.av_waitrequest        (1'b0),                                                                 //              (terminated)
		.av_writebyteenable    (),                                                                     //              (terminated)
		.av_lock               (),                                                                     //              (terminated)
		.av_chipselect         (),                                                                     //              (terminated)
		.av_clken              (),                                                                     //              (terminated)
		.uav_clken             (1'b0),                                                                 //              (terminated)
		.av_debugaccess        (),                                                                     //              (terminated)
		.av_outputenable       ()                                                                      //              (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pcie_hard_ip_0_bar2_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                       //                       clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                     //                     reset.reset
		.uav_address           (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (pcie_hard_ip_0_bar2_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (pcie_hard_ip_0_bar2_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (pcie_hard_ip_0_bar2_burstcount),                                         //                          .burstcount
		.av_byteenable         (pcie_hard_ip_0_bar2_byteenable),                                         //                          .byteenable
		.av_read               (pcie_hard_ip_0_bar2_read),                                               //                          .read
		.av_readdata           (pcie_hard_ip_0_bar2_readdata),                                           //                          .readdata
		.av_readdatavalid      (pcie_hard_ip_0_bar2_readdatavalid),                                      //                          .readdatavalid
		.av_write              (pcie_hard_ip_0_bar2_write),                                              //                          .write
		.av_writedata          (pcie_hard_ip_0_bar2_writedata),                                          //                          .writedata
		.av_beginbursttransfer (1'b0),                                                                   //               (terminated)
		.av_begintransfer      (1'b0),                                                                   //               (terminated)
		.av_chipselect         (1'b0),                                                                   //               (terminated)
		.av_lock               (1'b0),                                                                   //               (terminated)
		.av_debugaccess        (1'b0),                                                                   //               (terminated)
		.uav_clken             (),                                                                       //               (terminated)
		.av_clken              (1'b1)                                                                    //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pcie_hard_ip_0_cra_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                              //                      clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                            //                    reset.reset
		.uav_address           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_waitrequest        (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_chipselect         (pcie_hard_ip_0_cra_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) modular_sgdma_dispatcher_0_csr_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                                          //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                            //                    reset.reset
		.uav_address           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (modular_sgdma_dispatcher_0_csr_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_begintransfer      (),                                                                                          //              (terminated)
		.av_beginbursttransfer (),                                                                                          //              (terminated)
		.av_burstcount         (),                                                                                          //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                      //              (terminated)
		.av_waitrequest        (1'b0),                                                                                      //              (terminated)
		.av_writebyteenable    (),                                                                                          //              (terminated)
		.av_lock               (),                                                                                          //              (terminated)
		.av_chipselect         (),                                                                                          //              (terminated)
		.av_clken              (),                                                                                          //              (terminated)
		.uav_clken             (1'b0),                                                                                      //              (terminated)
		.av_debugaccess        (),                                                                                          //              (terminated)
		.av_outputenable       ()                                                                                           //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (128),
		.UAV_DATA_W                     (128),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (16),
		.UAV_BYTEENABLE_W               (16),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (5),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (16),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) modular_sgdma_dispatcher_0_descriptor_slave_translator (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),                                                                                                      //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                                                                        //                    reset.reset
		.uav_address           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_address),                                      // avalon_universal_slave_0.address
		.uav_burstcount        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),                                   //                         .burstcount
		.uav_read              (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_read),                                         //                         .read
		.uav_write             (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_write),                                        //                         .write
		.uav_waitrequest       (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),                                  //                         .waitrequest
		.uav_readdatavalid     (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),                                //                         .readdatavalid
		.uav_byteenable        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),                                   //                         .byteenable
		.uav_readdata          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                                     //                         .readdata
		.uav_writedata         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_writedata),                                    //                         .writedata
		.uav_lock              (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_lock),                                         //                         .lock
		.uav_debugaccess       (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),                                  //                         .debugaccess
		.av_write              (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_write),                                                      //      avalon_anti_slave_0.write
		.av_writedata          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_writedata),                                                  //                         .writedata
		.av_byteenable         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_byteenable),                                                 //                         .byteenable
		.av_waitrequest        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_anti_slave_0_waitrequest),                                                //                         .waitrequest
		.av_address            (),                                                                                                                                      //              (terminated)
		.av_read               (),                                                                                                                                      //              (terminated)
		.av_readdata           (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011011110101011011101111010101101), //              (terminated)
		.av_begintransfer      (),                                                                                                                                      //              (terminated)
		.av_beginbursttransfer (),                                                                                                                                      //              (terminated)
		.av_burstcount         (),                                                                                                                                      //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                                                                  //              (terminated)
		.av_writebyteenable    (),                                                                                                                                      //              (terminated)
		.av_lock               (),                                                                                                                                      //              (terminated)
		.av_chipselect         (),                                                                                                                                      //              (terminated)
		.av_clken              (),                                                                                                                                      //              (terminated)
		.uav_clken             (1'b0),                                                                                                                                  //              (terminated)
		.av_debugaccess        (),                                                                                                                                      //              (terminated)
		.av_outputenable       ()                                                                                                                                       //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_BEGIN_BURST           (137),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.PKT_BURST_TYPE_H          (134),
		.PKT_BURST_TYPE_L          (133),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_THREAD_ID_H           (143),
		.PKT_THREAD_ID_L           (143),
		.PKT_CACHE_H               (150),
		.PKT_CACHE_L               (147),
		.PKT_DATA_SIDEBAND_H       (136),
		.PKT_DATA_SIDEBAND_L       (136),
		.PKT_QOS_H                 (138),
		.PKT_QOS_L                 (138),
		.PKT_ADDR_SIDEBAND_H       (135),
		.PKT_ADDR_SIDEBAND_L       (135),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (8),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1023),
		.CACHE_VALUE               (4'b0000)
	) dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent (
		.clk              (pcie_hard_ip_0_pcie_core_clk_clk),                                                                 //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                                   // clk_reset.reset
		.av_address       (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (rsp_xbar_mux_src_valid),                                                                           //        rp.valid
		.rp_data          (rsp_xbar_mux_src_data),                                                                            //          .data
		.rp_channel       (rsp_xbar_mux_src_channel),                                                                         //          .channel
		.rp_startofpacket (rsp_xbar_mux_src_startofpacket),                                                                   //          .startofpacket
		.rp_endofpacket   (rsp_xbar_mux_src_endofpacket),                                                                     //          .endofpacket
		.rp_ready         (rsp_xbar_mux_src_ready)                                                                            //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_BEGIN_BURST           (137),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.PKT_BURST_TYPE_H          (134),
		.PKT_BURST_TYPE_L          (133),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_THREAD_ID_H           (143),
		.PKT_THREAD_ID_L           (143),
		.PKT_CACHE_H               (150),
		.PKT_CACHE_L               (147),
		.PKT_DATA_SIDEBAND_H       (136),
		.PKT_DATA_SIDEBAND_L       (136),
		.PKT_QOS_H                 (138),
		.PKT_QOS_L                 (138),
		.PKT_ADDR_SIDEBAND_H       (135),
		.PKT_ADDR_SIDEBAND_L       (135),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (8),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1023),
		.CACHE_VALUE               (4'b0000)
	) dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent (
		.clk              (pcie_hard_ip_0_pcie_core_clk_clk),                                                               //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                                 // clk_reset.reset
		.av_address       (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_rsp_src_valid),                                                                          //        rp.valid
		.rp_data          (limiter_rsp_src_data),                                                                           //          .data
		.rp_channel       (limiter_rsp_src_channel),                                                                        //          .channel
		.rp_startofpacket (limiter_rsp_src_startofpacket),                                                                  //          .startofpacket
		.rp_endofpacket   (limiter_rsp_src_endofpacket),                                                                    //          .endofpacket
		.rp_ready         (limiter_rsp_src_ready)                                                                           //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_BEGIN_BURST           (137),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.PKT_BURST_TYPE_H          (134),
		.PKT_BURST_TYPE_L          (133),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_THREAD_ID_H           (143),
		.PKT_THREAD_ID_L           (143),
		.PKT_CACHE_H               (150),
		.PKT_CACHE_L               (147),
		.PKT_DATA_SIDEBAND_H       (136),
		.PKT_DATA_SIDEBAND_L       (136),
		.PKT_QOS_H                 (138),
		.PKT_QOS_L                 (138),
		.PKT_ADDR_SIDEBAND_H       (135),
		.PKT_ADDR_SIDEBAND_L       (135),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (1023),
		.CACHE_VALUE               (4'b0000)
	) pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent (
		.clk              (pcie_hard_ip_0_pcie_core_clk_clk),                                                  //       clk.clk
		.reset            (rst_controller_001_reset_out_reset),                                                // clk_reset.reset
		.av_address       (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_001_rsp_src_valid),                                                         //        rp.valid
		.rp_data          (limiter_001_rsp_src_data),                                                          //          .data
		.rp_channel       (limiter_001_rsp_src_channel),                                                       //          .channel
		.rp_startofpacket (limiter_001_rsp_src_startofpacket),                                                 //          .startofpacket
		.rp_endofpacket   (limiter_001_rsp_src_endofpacket),                                                   //          .endofpacket
		.rp_ready         (limiter_001_rsp_src_ready)                                                          //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (137),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_RESPONSE_STATUS_H     (152),
		.PKT_RESPONSE_STATUS_L     (151),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (153),
		.AVS_BURSTCOUNT_W          (4),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                         //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                           //       clk_reset.reset
		.m0_address              (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                                                             //              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                                                             //                .valid
		.cp_data                 (agent_pipeline_source0_data),                                                              //                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),                                                     //                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),                                                       //                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                                                           //                .channel
		.rf_sink_ready           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (154),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                         //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                           // clk_reset.reset
		.in_data           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                    // (terminated)
		.csr_read          (1'b0),                                                                                     // (terminated)
		.csr_write         (1'b0),                                                                                     // (terminated)
		.csr_readdata      (),                                                                                         // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
		.almost_full_data  (),                                                                                         // (terminated)
		.almost_empty_data (),                                                                                         // (terminated)
		.in_empty          (1'b0),                                                                                     // (terminated)
		.out_empty         (),                                                                                         // (terminated)
		.in_error          (1'b0),                                                                                     // (terminated)
		.out_error         (),                                                                                         // (terminated)
		.in_channel        (1'b0),                                                                                     // (terminated)
		.out_channel       ()                                                                                          // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (137),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_RESPONSE_STATUS_H     (152),
		.PKT_RESPONSE_STATUS_L     (151),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (153),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                        //             clk.clk
		.reset                   (rst_controller_001_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_002_source0_ready),                                                        //              cp.ready
		.cp_valid                (agent_pipeline_002_source0_valid),                                                        //                .valid
		.cp_data                 (agent_pipeline_002_source0_data),                                                         //                .data
		.cp_startofpacket        (agent_pipeline_002_source0_startofpacket),                                                //                .startofpacket
		.cp_endofpacket          (agent_pipeline_002_source0_endofpacket),                                                  //                .endofpacket
		.cp_channel              (agent_pipeline_002_source0_channel),                                                      //                .channel
		.rf_sink_ready           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (154),
		.FIFO_DEPTH          (9),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                        //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (101),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (104),
		.PKT_SRC_ID_L              (103),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (105),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (117),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pio_led_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                  //       clk_reset.reset
		.m0_address              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_004_source0_ready),                                                //              cp.ready
		.cp_valid                (agent_pipeline_004_source0_valid),                                                //                .valid
		.cp_data                 (agent_pipeline_004_source0_data),                                                 //                .data
		.cp_startofpacket        (agent_pipeline_004_source0_startofpacket),                                        //                .startofpacket
		.cp_endofpacket          (agent_pipeline_004_source0_endofpacket),                                          //                .endofpacket
		.cp_channel              (agent_pipeline_004_source0_channel),                                              //                .channel
		.rf_sink_ready           (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (118),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                  // clk_reset.reset
		.in_data           (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                           // (terminated)
		.csr_read          (1'b0),                                                                            // (terminated)
		.csr_write         (1'b0),                                                                            // (terminated)
		.csr_readdata      (),                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                            // (terminated)
		.almost_full_data  (),                                                                                // (terminated)
		.almost_empty_data (),                                                                                // (terminated)
		.in_empty          (1'b0),                                                                            // (terminated)
		.out_empty         (),                                                                                // (terminated)
		.in_error          (1'b0),                                                                            // (terminated)
		.out_error         (),                                                                                // (terminated)
		.in_channel        (1'b0),                                                                            // (terminated)
		.out_channel       ()                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (101),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (104),
		.PKT_SRC_ID_L              (103),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (105),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (117),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pio_pb_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                               //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                 //       clk_reset.reset
		.m0_address              (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pio_pb_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_006_source0_ready),                                               //              cp.ready
		.cp_valid                (agent_pipeline_006_source0_valid),                                               //                .valid
		.cp_data                 (agent_pipeline_006_source0_data),                                                //                .data
		.cp_startofpacket        (agent_pipeline_006_source0_startofpacket),                                       //                .startofpacket
		.cp_endofpacket          (agent_pipeline_006_source0_endofpacket),                                         //                .endofpacket
		.cp_channel              (agent_pipeline_006_source0_channel),                                             //                .channel
		.rf_sink_ready           (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pio_pb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (118),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                               //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                 // clk_reset.reset
		.in_data           (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pio_pb_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pio_pb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                          // (terminated)
		.csr_read          (1'b0),                                                                           // (terminated)
		.csr_write         (1'b0),                                                                           // (terminated)
		.csr_readdata      (),                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                           // (terminated)
		.almost_full_data  (),                                                                               // (terminated)
		.almost_empty_data (),                                                                               // (terminated)
		.in_empty          (1'b0),                                                                           // (terminated)
		.out_empty         (),                                                                               // (terminated)
		.in_error          (1'b0),                                                                           // (terminated)
		.out_error         (),                                                                               // (terminated)
		.in_channel        (1'b0),                                                                           // (terminated)
		.out_channel       ()                                                                                // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (146),
		.PKT_PROTECTION_L          (144),
		.PKT_BEGIN_BURST           (137),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.PKT_BURST_TYPE_H          (134),
		.PKT_BURST_TYPE_L          (133),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (140),
		.PKT_SRC_ID_L              (139),
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_THREAD_ID_H           (143),
		.PKT_THREAD_ID_L           (143),
		.PKT_CACHE_H               (150),
		.PKT_CACHE_L               (147),
		.PKT_DATA_SIDEBAND_H       (136),
		.PKT_DATA_SIDEBAND_L       (136),
		.PKT_QOS_H                 (138),
		.PKT_QOS_L                 (138),
		.PKT_ADDR_SIDEBAND_H       (135),
		.PKT_ADDR_SIDEBAND_L       (135),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (3),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1023),
		.CACHE_VALUE               (4'b0000)
	) pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent (
		.clk              (pcie_hard_ip_0_pcie_core_clk_clk),                                                //       clk.clk
		.reset            (rst_controller_001_reset_out_reset),                                              // clk_reset.reset
		.av_address       (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_002_rsp_src_valid),                                                       //        rp.valid
		.rp_data          (limiter_002_rsp_src_data),                                                        //          .data
		.rp_channel       (limiter_002_rsp_src_channel),                                                     //          .channel
		.rp_startofpacket (limiter_002_rsp_src_startofpacket),                                               //          .startofpacket
		.rp_endofpacket   (limiter_002_rsp_src_endofpacket),                                                 //          .endofpacket
		.rp_ready         (limiter_002_rsp_src_ready)                                                        //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (101),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (104),
		.PKT_SRC_ID_L              (103),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (105),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.ST_CHANNEL_W              (3),
		.ST_DATA_W                 (117),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                        //             clk.clk
		.reset                   (rst_controller_001_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_008_source0_ready),                                                        //              cp.ready
		.cp_valid                (agent_pipeline_008_source0_valid),                                                        //                .valid
		.cp_data                 (agent_pipeline_008_source0_data),                                                         //                .data
		.cp_startofpacket        (agent_pipeline_008_source0_startofpacket),                                                //                .startofpacket
		.cp_endofpacket          (agent_pipeline_008_source0_endofpacket),                                                  //                .endofpacket
		.cp_channel              (agent_pipeline_008_source0_channel),                                                      //                .channel
		.rf_sink_ready           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (118),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                        //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (101),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (104),
		.PKT_SRC_ID_L              (103),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (105),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.ST_CHANNEL_W              (3),
		.ST_DATA_W                 (117),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1)
	) modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                                    //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                      //       clk_reset.reset
		.m0_address              (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_010_source0_ready),                                                                    //              cp.ready
		.cp_valid                (agent_pipeline_010_source0_valid),                                                                    //                .valid
		.cp_data                 (agent_pipeline_010_source0_data),                                                                     //                .data
		.cp_startofpacket        (agent_pipeline_010_source0_startofpacket),                                                            //                .startofpacket
		.cp_endofpacket          (agent_pipeline_010_source0_endofpacket),                                                              //                .endofpacket
		.cp_channel              (agent_pipeline_010_source0_channel),                                                                  //                .channel
		.rf_sink_ready           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (118),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                                    //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                      // clk_reset.reset
		.in_data           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                               // (terminated)
		.csr_read          (1'b0),                                                                                                // (terminated)
		.csr_write         (1'b0),                                                                                                // (terminated)
		.csr_readdata      (),                                                                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                                // (terminated)
		.almost_full_data  (),                                                                                                    // (terminated)
		.almost_empty_data (),                                                                                                    // (terminated)
		.in_empty          (1'b0),                                                                                                // (terminated)
		.out_empty         (),                                                                                                    // (terminated)
		.in_error          (1'b0),                                                                                                // (terminated)
		.out_error         (),                                                                                                    // (terminated)
		.in_channel        (1'b0),                                                                                                // (terminated)
		.out_channel       ()                                                                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (127),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (209),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (143),
		.PKT_BYTEEN_L              (128),
		.PKT_ADDR_H                (175),
		.PKT_ADDR_L                (144),
		.PKT_TRANS_COMPRESSED_READ (176),
		.PKT_TRANS_POSTED          (177),
		.PKT_TRANS_WRITE           (178),
		.PKT_TRANS_READ            (179),
		.PKT_TRANS_LOCK            (180),
		.PKT_SRC_ID_H              (212),
		.PKT_SRC_ID_L              (211),
		.PKT_DEST_ID_H             (214),
		.PKT_DEST_ID_L             (213),
		.PKT_BURSTWRAP_H           (201),
		.PKT_BURSTWRAP_L           (192),
		.PKT_BYTE_CNT_H            (191),
		.PKT_BYTE_CNT_L            (182),
		.PKT_PROTECTION_H          (218),
		.PKT_PROTECTION_L          (216),
		.PKT_RESPONSE_STATUS_H     (224),
		.PKT_RESPONSE_STATUS_L     (223),
		.PKT_BURST_SIZE_H          (204),
		.PKT_BURST_SIZE_L          (202),
		.ST_CHANNEL_W              (3),
		.ST_DATA_W                 (225),
		.AVS_BURSTCOUNT_W          (5),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent (
		.clk                     (pcie_hard_ip_0_pcie_core_clk_clk),                                                                                 //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                                   //       clk_reset.reset
		.m0_address              (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_012_source0_ready),                                                                                 //              cp.ready
		.cp_valid                (agent_pipeline_012_source0_valid),                                                                                 //                .valid
		.cp_data                 (agent_pipeline_012_source0_data),                                                                                  //                .data
		.cp_startofpacket        (agent_pipeline_012_source0_startofpacket),                                                                         //                .startofpacket
		.cp_endofpacket          (agent_pipeline_012_source0_endofpacket),                                                                           //                .endofpacket
		.cp_channel              (agent_pipeline_012_source0_channel),                                                                               //                .channel
		.rf_sink_ready           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (226),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                                                 //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                                   // clk_reset.reset
		.in_data           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                                             // (terminated)
		.almost_full_data  (),                                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                                             // (terminated)
		.out_empty         (),                                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                                             // (terminated)
		.out_error         (),                                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                                             // (terminated)
		.out_channel       ()                                                                                                                  // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (128),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                                           //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                             // clk_reset.reset
		.in_data           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                                                      // (terminated)
		.csr_read          (1'b0),                                                                                                       // (terminated)
		.csr_write         (1'b0),                                                                                                       // (terminated)
		.csr_readdata      (),                                                                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                                       // (terminated)
		.almost_full_data  (),                                                                                                           // (terminated)
		.almost_empty_data (),                                                                                                           // (terminated)
		.in_startofpacket  (1'b0),                                                                                                       // (terminated)
		.in_endofpacket    (1'b0),                                                                                                       // (terminated)
		.out_startofpacket (),                                                                                                           // (terminated)
		.out_endofpacket   (),                                                                                                           // (terminated)
		.in_empty          (1'b0),                                                                                                       // (terminated)
		.out_empty         (),                                                                                                           // (terminated)
		.in_error          (1'b0),                                                                                                       // (terminated)
		.out_error         (),                                                                                                           // (terminated)
		.in_channel        (1'b0),                                                                                                       // (terminated)
		.out_channel       ()                                                                                                            // (terminated)
	);

	q_sys_addr_router addr_router (
		.sink_ready         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (dma_write_master_0_data_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),                                                                 //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                                   // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                                            //       src.ready
		.src_valid          (addr_router_src_valid),                                                                            //          .valid
		.src_data           (addr_router_src_data),                                                                             //          .data
		.src_channel        (addr_router_src_channel),                                                                          //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                                    //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                                       //          .endofpacket
	);

	q_sys_addr_router addr_router_001 (
		.sink_ready         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (dma_read_master_0_data_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),                                                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                                 // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                                      //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                                      //          .valid
		.src_data           (addr_router_001_src_data),                                                                       //          .data
		.src_channel        (addr_router_001_src_channel),                                                                    //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                                              //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                                                 //          .endofpacket
	);

	q_sys_addr_router_002 addr_router_002 (
		.sink_ready         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (pcie_hard_ip_0_bar1_0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),                                                  //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),                                                // clk_reset.reset
		.src_ready          (addr_router_002_src_ready),                                                         //       src.ready
		.src_valid          (addr_router_002_src_valid),                                                         //          .valid
		.src_data           (addr_router_002_src_data),                                                          //          .data
		.src_channel        (addr_router_002_src_channel),                                                       //          .channel
		.src_startofpacket  (addr_router_002_src_startofpacket),                                                 //          .startofpacket
		.src_endofpacket    (addr_router_002_src_endofpacket)                                                    //          .endofpacket
	);

	q_sys_id_router id_router (
		.sink_ready         (agent_pipeline_001_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_001_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_reset_out_reset),           // clk_reset.reset
		.src_ready          (id_router_src_ready),                      //       src.ready
		.src_valid          (id_router_src_valid),                      //          .valid
		.src_data           (id_router_src_data),                       //          .data
		.src_channel        (id_router_src_channel),                    //          .channel
		.src_startofpacket  (id_router_src_startofpacket),              //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                 //          .endofpacket
	);

	q_sys_id_router_001 id_router_001 (
		.sink_ready         (agent_pipeline_003_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_003_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),       // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                  //       src.ready
		.src_valid          (id_router_001_src_valid),                  //          .valid
		.src_data           (id_router_001_src_data),                   //          .data
		.src_channel        (id_router_001_src_channel),                //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)             //          .endofpacket
	);

	q_sys_id_router_002 id_router_002 (
		.sink_ready         (agent_pipeline_005_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_005_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_005_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_005_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_005_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_reset_out_reset),           // clk_reset.reset
		.src_ready          (id_router_002_src_ready),                  //       src.ready
		.src_valid          (id_router_002_src_valid),                  //          .valid
		.src_data           (id_router_002_src_data),                   //          .data
		.src_channel        (id_router_002_src_channel),                //          .channel
		.src_startofpacket  (id_router_002_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_002_src_endofpacket)             //          .endofpacket
	);

	q_sys_id_router_002 id_router_003 (
		.sink_ready         (agent_pipeline_007_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_007_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_007_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_007_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_007_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_reset_out_reset),           // clk_reset.reset
		.src_ready          (id_router_003_src_ready),                  //       src.ready
		.src_valid          (id_router_003_src_valid),                  //          .valid
		.src_data           (id_router_003_src_data),                   //          .data
		.src_channel        (id_router_003_src_channel),                //          .channel
		.src_startofpacket  (id_router_003_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_003_src_endofpacket)             //          .endofpacket
	);

	q_sys_addr_router_003 addr_router_003 (
		.sink_ready         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (pcie_hard_ip_0_bar2_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),                                                //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),                                              // clk_reset.reset
		.src_ready          (addr_router_003_src_ready),                                                       //       src.ready
		.src_valid          (addr_router_003_src_valid),                                                       //          .valid
		.src_data           (addr_router_003_src_data),                                                        //          .data
		.src_channel        (addr_router_003_src_channel),                                                     //          .channel
		.src_startofpacket  (addr_router_003_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (addr_router_003_src_endofpacket)                                                  //          .endofpacket
	);

	q_sys_id_router_004 id_router_004 (
		.sink_ready         (agent_pipeline_009_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_009_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_009_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_009_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_009_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),       // clk_reset.reset
		.src_ready          (id_router_004_src_ready),                  //       src.ready
		.src_valid          (id_router_004_src_valid),                  //          .valid
		.src_data           (id_router_004_src_data),                   //          .data
		.src_channel        (id_router_004_src_channel),                //          .channel
		.src_startofpacket  (id_router_004_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_004_src_endofpacket)             //          .endofpacket
	);

	q_sys_id_router_004 id_router_005 (
		.sink_ready         (agent_pipeline_011_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_011_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_011_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_011_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_011_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_reset_out_reset),           // clk_reset.reset
		.src_ready          (id_router_005_src_ready),                  //       src.ready
		.src_valid          (id_router_005_src_valid),                  //          .valid
		.src_data           (id_router_005_src_data),                   //          .data
		.src_channel        (id_router_005_src_channel),                //          .channel
		.src_startofpacket  (id_router_005_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_005_src_endofpacket)             //          .endofpacket
	);

	q_sys_id_router_006 id_router_006 (
		.sink_ready         (agent_pipeline_013_source0_ready),         //      sink.ready
		.sink_valid         (agent_pipeline_013_source0_valid),         //          .valid
		.sink_data          (agent_pipeline_013_source0_data),          //          .data
		.sink_startofpacket (agent_pipeline_013_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (agent_pipeline_013_source0_endofpacket),   //          .endofpacket
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),         //       clk.clk
		.reset              (rst_controller_reset_out_reset),           // clk_reset.reset
		.src_ready          (id_router_006_src_ready),                  //       src.ready
		.src_valid          (id_router_006_src_valid),                  //          .valid
		.src_data           (id_router_006_src_data),                   //          .data
		.src_channel        (id_router_006_src_channel),                //          .channel
		.src_startofpacket  (id_router_006_src_startofpacket),          //          .startofpacket
		.src_endofpacket    (id_router_006_src_endofpacket)             //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.MAX_OUTSTANDING_RESPONSES (20),
		.PIPELINED                 (0),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64)
	) limiter (
		.clk                    (pcie_hard_ip_0_pcie_core_clk_clk),           //       clk.clk
		.reset                  (rst_controller_reset_out_reset),             // clk_reset.reset
		.cmd_sink_ready         (addr_router_001_src_ready),                  //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_001_src_valid),                  //          .valid
		.cmd_sink_data          (addr_router_001_src_data),                   //          .data
		.cmd_sink_channel       (addr_router_001_src_channel),                //          .channel
		.cmd_sink_startofpacket (addr_router_001_src_startofpacket),          //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_001_src_endofpacket),            //          .endofpacket
		.cmd_src_ready          (limiter_cmd_src_ready),                      //   cmd_src.ready
		.cmd_src_data           (limiter_cmd_src_data),                       //          .data
		.cmd_src_channel        (limiter_cmd_src_channel),                    //          .channel
		.cmd_src_startofpacket  (limiter_cmd_src_startofpacket),              //          .startofpacket
		.cmd_src_endofpacket    (limiter_cmd_src_endofpacket),                //          .endofpacket
		.cmd_src_valid          (limiter_cmd_src_valid),                      //          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),         //          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),       //          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),          //          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_rsp_src_ready),                      //   rsp_src.ready
		.rsp_src_valid          (limiter_rsp_src_valid),                      //          .valid
		.rsp_src_data           (limiter_rsp_src_data),                       //          .data
		.rsp_src_channel        (limiter_rsp_src_channel),                    //          .channel
		.rsp_src_startofpacket  (limiter_rsp_src_startofpacket),              //          .startofpacket
		.rsp_src_endofpacket    (limiter_rsp_src_endofpacket)                 //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.MAX_OUTSTANDING_RESPONSES (15),
		.PIPELINED                 (0),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64)
	) limiter_001 (
		.clk                    (pcie_hard_ip_0_pcie_core_clk_clk),           //       clk.clk
		.reset                  (rst_controller_001_reset_out_reset),         // clk_reset.reset
		.cmd_sink_ready         (addr_router_002_src_ready),                  //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_002_src_valid),                  //          .valid
		.cmd_sink_data          (addr_router_002_src_data),                   //          .data
		.cmd_sink_channel       (addr_router_002_src_channel),                //          .channel
		.cmd_sink_startofpacket (addr_router_002_src_startofpacket),          //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_002_src_endofpacket),            //          .endofpacket
		.cmd_src_ready          (limiter_001_cmd_src_ready),                  //   cmd_src.ready
		.cmd_src_data           (limiter_001_cmd_src_data),                   //          .data
		.cmd_src_channel        (limiter_001_cmd_src_channel),                //          .channel
		.cmd_src_startofpacket  (limiter_001_cmd_src_startofpacket),          //          .startofpacket
		.cmd_src_endofpacket    (limiter_001_cmd_src_endofpacket),            //          .endofpacket
		.cmd_src_valid          (limiter_001_cmd_src_valid),                  //          .valid
		.rsp_sink_ready         (limiter_pipeline_003_source0_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_003_source0_valid),         //          .valid
		.rsp_sink_channel       (limiter_pipeline_003_source0_channel),       //          .channel
		.rsp_sink_data          (limiter_pipeline_003_source0_data),          //          .data
		.rsp_sink_startofpacket (limiter_pipeline_003_source0_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_003_source0_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_001_rsp_src_ready),                  //   rsp_src.ready
		.rsp_src_valid          (limiter_001_rsp_src_valid),                  //          .valid
		.rsp_src_data           (limiter_001_rsp_src_data),                   //          .data
		.rsp_src_channel        (limiter_001_rsp_src_channel),                //          .channel
		.rsp_src_startofpacket  (limiter_001_rsp_src_startofpacket),          //          .startofpacket
		.rsp_src_endofpacket    (limiter_001_rsp_src_endofpacket)             //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (142),
		.PKT_DEST_ID_L             (141),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.MAX_OUTSTANDING_RESPONSES (15),
		.PIPELINED                 (0),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (3),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64)
	) limiter_002 (
		.clk                    (pcie_hard_ip_0_pcie_core_clk_clk),           //       clk.clk
		.reset                  (rst_controller_001_reset_out_reset),         // clk_reset.reset
		.cmd_sink_ready         (addr_router_003_src_ready),                  //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_003_src_valid),                  //          .valid
		.cmd_sink_data          (addr_router_003_src_data),                   //          .data
		.cmd_sink_channel       (addr_router_003_src_channel),                //          .channel
		.cmd_sink_startofpacket (addr_router_003_src_startofpacket),          //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_003_src_endofpacket),            //          .endofpacket
		.cmd_src_ready          (limiter_002_cmd_src_ready),                  //   cmd_src.ready
		.cmd_src_data           (limiter_002_cmd_src_data),                   //          .data
		.cmd_src_channel        (limiter_002_cmd_src_channel),                //          .channel
		.cmd_src_startofpacket  (limiter_002_cmd_src_startofpacket),          //          .startofpacket
		.cmd_src_endofpacket    (limiter_002_cmd_src_endofpacket),            //          .endofpacket
		.cmd_src_valid          (limiter_002_cmd_src_valid),                  //          .valid
		.rsp_sink_ready         (limiter_pipeline_005_source0_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_005_source0_valid),         //          .valid
		.rsp_sink_channel       (limiter_pipeline_005_source0_channel),       //          .channel
		.rsp_sink_data          (limiter_pipeline_005_source0_data),          //          .data
		.rsp_sink_startofpacket (limiter_pipeline_005_source0_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_005_source0_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_002_rsp_src_ready),                  //   rsp_src.ready
		.rsp_src_valid          (limiter_002_rsp_src_valid),                  //          .valid
		.rsp_src_data           (limiter_002_rsp_src_data),                   //          .data
		.rsp_src_channel        (limiter_002_rsp_src_channel),                //          .channel
		.rsp_src_startofpacket  (limiter_002_rsp_src_startofpacket),          //          .startofpacket
		.rsp_src_endofpacket    (limiter_002_rsp_src_endofpacket)             //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_BEGIN_BURST           (137),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_BURST_SIZE_H          (132),
		.PKT_BURST_SIZE_L          (130),
		.PKT_BURST_TYPE_H          (134),
		.PKT_BURST_TYPE_L          (133),
		.PKT_BURSTWRAP_H           (129),
		.PKT_BURSTWRAP_L           (120),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (153),
		.ST_CHANNEL_W              (4),
		.OUT_BYTE_CNT_H            (113),
		.OUT_BURSTWRAP_H           (129),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),    //       cr0.clk
		.reset                 (rst_controller_reset_out_reset),      // cr0_reset.reset
		.sink0_valid           (cmd_xbar_mux_src_valid),              //     sink0.valid
		.sink0_data            (cmd_xbar_mux_src_data),               //          .data
		.sink0_channel         (cmd_xbar_mux_src_channel),            //          .channel
		.sink0_startofpacket   (cmd_xbar_mux_src_startofpacket),      //          .startofpacket
		.sink0_endofpacket     (cmd_xbar_mux_src_endofpacket),        //          .endofpacket
		.sink0_ready           (cmd_xbar_mux_src_ready),              //          .ready
		.source0_valid         (burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_source0_data),          //          .data
		.source0_channel       (burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (101),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.PKT_BURST_TYPE_H          (98),
		.PKT_BURST_TYPE_L          (97),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (117),
		.ST_CHANNEL_W              (4),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (93),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter_001 (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),        //       cr0.clk
		.reset                 (rst_controller_reset_out_reset),          // cr0_reset.reset
		.sink0_valid           (width_adapter_src_valid),                 //     sink0.valid
		.sink0_data            (width_adapter_src_data),                  //          .data
		.sink0_channel         (width_adapter_src_channel),               //          .channel
		.sink0_startofpacket   (width_adapter_src_startofpacket),         //          .startofpacket
		.sink0_endofpacket     (width_adapter_src_endofpacket),           //          .endofpacket
		.sink0_ready           (width_adapter_src_ready),                 //          .ready
		.source0_valid         (burst_adapter_001_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_001_source0_data),          //          .data
		.source0_channel       (burst_adapter_001_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_001_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_001_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_001_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (101),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.PKT_BURST_TYPE_H          (98),
		.PKT_BURST_TYPE_L          (97),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (117),
		.ST_CHANNEL_W              (4),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (93),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter_002 (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),        //       cr0.clk
		.reset                 (rst_controller_reset_out_reset),          // cr0_reset.reset
		.sink0_valid           (width_adapter_002_src_valid),             //     sink0.valid
		.sink0_data            (width_adapter_002_src_data),              //          .data
		.sink0_channel         (width_adapter_002_src_channel),           //          .channel
		.sink0_startofpacket   (width_adapter_002_src_startofpacket),     //          .startofpacket
		.sink0_endofpacket     (width_adapter_002_src_endofpacket),       //          .endofpacket
		.sink0_ready           (width_adapter_002_src_ready),             //          .ready
		.source0_valid         (burst_adapter_002_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_002_source0_data),          //          .data
		.source0_channel       (burst_adapter_002_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_002_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_002_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_002_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (101),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.PKT_BURST_TYPE_H          (98),
		.PKT_BURST_TYPE_L          (97),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (117),
		.ST_CHANNEL_W              (3),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (93),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter_003 (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),        //       cr0.clk
		.reset                 (rst_controller_001_reset_out_reset),      // cr0_reset.reset
		.sink0_valid           (width_adapter_004_src_valid),             //     sink0.valid
		.sink0_data            (width_adapter_004_src_data),              //          .data
		.sink0_channel         (width_adapter_004_src_channel),           //          .channel
		.sink0_startofpacket   (width_adapter_004_src_startofpacket),     //          .startofpacket
		.sink0_endofpacket     (width_adapter_004_src_endofpacket),       //          .endofpacket
		.sink0_ready           (width_adapter_004_src_ready),             //          .ready
		.source0_valid         (burst_adapter_003_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_003_source0_data),          //          .data
		.source0_channel       (burst_adapter_003_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_003_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_003_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_003_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (101),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (96),
		.PKT_BURST_SIZE_L          (94),
		.PKT_BURST_TYPE_H          (98),
		.PKT_BURST_TYPE_L          (97),
		.PKT_BURSTWRAP_H           (93),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (117),
		.ST_CHANNEL_W              (3),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (93),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter_004 (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),        //       cr0.clk
		.reset                 (rst_controller_reset_out_reset),          // cr0_reset.reset
		.sink0_valid           (width_adapter_006_src_valid),             //     sink0.valid
		.sink0_data            (width_adapter_006_src_data),              //          .data
		.sink0_channel         (width_adapter_006_src_channel),           //          .channel
		.sink0_startofpacket   (width_adapter_006_src_startofpacket),     //          .startofpacket
		.sink0_endofpacket     (width_adapter_006_src_endofpacket),       //          .endofpacket
		.sink0_ready           (width_adapter_006_src_ready),             //          .ready
		.source0_valid         (burst_adapter_004_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_004_source0_data),          //          .data
		.source0_channel       (burst_adapter_004_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_004_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_004_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_004_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (175),
		.PKT_ADDR_L                (144),
		.PKT_BEGIN_BURST           (209),
		.PKT_BYTE_CNT_H            (191),
		.PKT_BYTE_CNT_L            (182),
		.PKT_BYTEEN_H              (143),
		.PKT_BYTEEN_L              (128),
		.PKT_BURST_SIZE_H          (204),
		.PKT_BURST_SIZE_L          (202),
		.PKT_BURST_TYPE_H          (206),
		.PKT_BURST_TYPE_L          (205),
		.PKT_BURSTWRAP_H           (201),
		.PKT_BURSTWRAP_L           (192),
		.PKT_TRANS_COMPRESSED_READ (176),
		.PKT_TRANS_WRITE           (178),
		.PKT_TRANS_READ            (179),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (225),
		.ST_CHANNEL_W              (3),
		.OUT_BYTE_CNT_H            (186),
		.OUT_BURSTWRAP_H           (201),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (0),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter_005 (
		.clk                   (pcie_hard_ip_0_pcie_core_clk_clk),        //       cr0.clk
		.reset                 (rst_controller_reset_out_reset),          // cr0_reset.reset
		.sink0_valid           (width_adapter_008_src_valid),             //     sink0.valid
		.sink0_data            (width_adapter_008_src_data),              //          .data
		.sink0_channel         (width_adapter_008_src_channel),           //          .channel
		.sink0_startofpacket   (width_adapter_008_src_startofpacket),     //          .startofpacket
		.sink0_endofpacket     (width_adapter_008_src_endofpacket),       //          .endofpacket
		.sink0_ready           (width_adapter_008_src_ready),             //          .ready
		.source0_valid         (burst_adapter_005_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_005_source0_data),          //          .data
		.source0_channel       (burst_adapter_005_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_005_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_005_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_005_source0_ready)          //          .ready
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),                   // reset_in0.reset
		.clk        (pcie_hard_ip_0_pcie_core_clk_clk), //       clk.clk
		.reset_out  (rst_controller_reset_out_reset),   // reset_out.reset
		.reset_in1  (1'b0),                             // (terminated)
		.reset_in2  (1'b0),                             // (terminated)
		.reset_in3  (1'b0),                             // (terminated)
		.reset_in4  (1'b0),                             // (terminated)
		.reset_in5  (1'b0),                             // (terminated)
		.reset_in6  (1'b0),                             // (terminated)
		.reset_in7  (1'b0),                             // (terminated)
		.reset_in8  (1'b0),                             // (terminated)
		.reset_in9  (1'b0),                             // (terminated)
		.reset_in10 (1'b0),                             // (terminated)
		.reset_in11 (1'b0),                             // (terminated)
		.reset_in12 (1'b0),                             // (terminated)
		.reset_in13 (1'b0),                             // (terminated)
		.reset_in14 (1'b0),                             // (terminated)
		.reset_in15 (1'b0)                              // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller_001 (
		.reset_in0  (~pcie_hard_ip_0_pcie_core_reset_reset), // reset_in0.reset
		.clk        (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset_out  (rst_controller_001_reset_out_reset),    // reset_out.reset
		.reset_in1  (1'b0),                                  // (terminated)
		.reset_in2  (1'b0),                                  // (terminated)
		.reset_in3  (1'b0),                                  // (terminated)
		.reset_in4  (1'b0),                                  // (terminated)
		.reset_in5  (1'b0),                                  // (terminated)
		.reset_in6  (1'b0),                                  // (terminated)
		.reset_in7  (1'b0),                                  // (terminated)
		.reset_in8  (1'b0),                                  // (terminated)
		.reset_in9  (1'b0),                                  // (terminated)
		.reset_in10 (1'b0),                                  // (terminated)
		.reset_in11 (1'b0),                                  // (terminated)
		.reset_in12 (1'b0),                                  // (terminated)
		.reset_in13 (1'b0),                                  // (terminated)
		.reset_in14 (1'b0),                                  // (terminated)
		.reset_in15 (1'b0)                                   // (terminated)
	);

	q_sys_cmd_xbar_demux cmd_xbar_demux (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),  //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (addr_router_src_ready),             //      sink.ready
		.sink_channel       (addr_router_src_channel),           //          .channel
		.sink_data          (addr_router_src_data),              //          .data
		.sink_startofpacket (addr_router_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),   //          .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),         //      src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),         //          .valid
		.src1_data          (cmd_xbar_demux_src1_data),          //          .data
		.src1_channel       (cmd_xbar_demux_src1_channel),       //          .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket)    //          .endofpacket
	);

	q_sys_cmd_xbar_demux cmd_xbar_demux_001 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset              (rst_controller_reset_out_reset),         // clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),         //      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),       //          .channel
		.sink_data          (limiter_pipeline_source0_data),          //          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),   //          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),         //          .valid
		.src0_ready         (cmd_xbar_demux_001_src0_ready),          //      src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),          //          .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),           //          .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),        //          .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket),  //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),    //          .endofpacket
		.src1_ready         (cmd_xbar_demux_001_src1_ready),          //      src1.ready
		.src1_valid         (cmd_xbar_demux_001_src1_valid),          //          .valid
		.src1_data          (cmd_xbar_demux_001_src1_data),           //          .data
		.src1_channel       (cmd_xbar_demux_001_src1_channel),        //          .channel
		.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket),  //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)     //          .endofpacket
	);

	q_sys_cmd_xbar_demux_002 cmd_xbar_demux_002 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),           //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),         // clk_reset.reset
		.sink_ready         (limiter_pipeline_002_source0_ready),         //      sink.ready
		.sink_channel       (limiter_pipeline_002_source0_channel),       //          .channel
		.sink_data          (limiter_pipeline_002_source0_data),          //          .data
		.sink_startofpacket (limiter_pipeline_002_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (limiter_pipeline_002_source0_endofpacket),   //          .endofpacket
		.sink_valid         (limiter_pipeline_002_source0_valid),         //          .valid
		.src0_ready         (cmd_xbar_demux_002_src0_ready),              //      src0.ready
		.src0_valid         (cmd_xbar_demux_002_src0_valid),              //          .valid
		.src0_data          (cmd_xbar_demux_002_src0_data),               //          .data
		.src0_channel       (cmd_xbar_demux_002_src0_channel),            //          .channel
		.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_002_src0_endofpacket),        //          .endofpacket
		.src1_ready         (cmd_xbar_demux_002_src1_ready),              //      src1.ready
		.src1_valid         (cmd_xbar_demux_002_src1_valid),              //          .valid
		.src1_data          (cmd_xbar_demux_002_src1_data),               //          .data
		.src1_channel       (cmd_xbar_demux_002_src1_channel),            //          .channel
		.src1_startofpacket (cmd_xbar_demux_002_src1_startofpacket),      //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_002_src1_endofpacket),        //          .endofpacket
		.src2_ready         (cmd_xbar_demux_002_src2_ready),              //      src2.ready
		.src2_valid         (cmd_xbar_demux_002_src2_valid),              //          .valid
		.src2_data          (cmd_xbar_demux_002_src2_data),               //          .data
		.src2_channel       (cmd_xbar_demux_002_src2_channel),            //          .channel
		.src2_startofpacket (cmd_xbar_demux_002_src2_startofpacket),      //          .startofpacket
		.src2_endofpacket   (cmd_xbar_demux_002_src2_endofpacket)         //          .endofpacket
	);

	q_sys_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_reset_out_reset),         // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                 //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                 //          .valid
		.src_data            (cmd_xbar_mux_src_data),                  //          .data
		.src_channel         (cmd_xbar_mux_src_channel),               //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),           //          .endofpacket
		.sink0_ready         (mux_pipeline_source0_ready),             //     sink0.ready
		.sink0_valid         (mux_pipeline_source0_valid),             //          .valid
		.sink0_channel       (mux_pipeline_source0_channel),           //          .channel
		.sink0_data          (mux_pipeline_source0_data),              //          .data
		.sink0_startofpacket (mux_pipeline_source0_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_source0_endofpacket),       //          .endofpacket
		.sink1_ready         (mux_pipeline_001_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_001_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_001_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_001_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_001_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_001_source0_endofpacket),   //          .endofpacket
		.sink2_ready         (mux_pipeline_002_source0_ready),         //     sink2.ready
		.sink2_valid         (mux_pipeline_002_source0_valid),         //          .valid
		.sink2_channel       (mux_pipeline_002_source0_channel),       //          .channel
		.sink2_data          (mux_pipeline_002_source0_data),          //          .data
		.sink2_startofpacket (mux_pipeline_002_source0_startofpacket), //          .startofpacket
		.sink2_endofpacket   (mux_pipeline_002_source0_endofpacket)    //          .endofpacket
	);

	q_sys_cmd_xbar_mux_001 cmd_xbar_mux_001 (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_001_reset_out_reset),     // clk_reset.reset
		.src_ready           (cmd_xbar_mux_001_src_ready),             //       src.ready
		.src_valid           (cmd_xbar_mux_001_src_valid),             //          .valid
		.src_data            (cmd_xbar_mux_001_src_data),              //          .data
		.src_channel         (cmd_xbar_mux_001_src_channel),           //          .channel
		.src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),     //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),       //          .endofpacket
		.sink0_ready         (mux_pipeline_003_source0_ready),         //     sink0.ready
		.sink0_valid         (mux_pipeline_003_source0_valid),         //          .valid
		.sink0_channel       (mux_pipeline_003_source0_channel),       //          .channel
		.sink0_data          (mux_pipeline_003_source0_data),          //          .data
		.sink0_startofpacket (mux_pipeline_003_source0_startofpacket), //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_003_source0_endofpacket),   //          .endofpacket
		.sink1_ready         (mux_pipeline_004_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_004_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_004_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_004_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_004_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_004_source0_endofpacket)    //          .endofpacket
	);

	q_sys_cmd_xbar_demux_002 rsp_xbar_demux (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),  //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_src_ready),               //      sink.ready
		.sink_channel       (id_router_src_channel),             //          .channel
		.sink_data          (id_router_src_data),                //          .data
		.sink_startofpacket (id_router_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),   //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),         //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),         //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),          //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),       //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket),   //          .endofpacket
		.src2_ready         (rsp_xbar_demux_src2_ready),         //      src2.ready
		.src2_valid         (rsp_xbar_demux_src2_valid),         //          .valid
		.src2_data          (rsp_xbar_demux_src2_data),          //          .data
		.src2_channel       (rsp_xbar_demux_src2_channel),       //          .channel
		.src2_startofpacket (rsp_xbar_demux_src2_startofpacket), //          .startofpacket
		.src2_endofpacket   (rsp_xbar_demux_src2_endofpacket)    //          .endofpacket
	);

	q_sys_cmd_xbar_demux rsp_xbar_demux_001 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_001_src_ready),               //      sink.ready
		.sink_channel       (id_router_001_src_channel),             //          .channel
		.sink_data          (id_router_001_src_data),                //          .data
		.sink_startofpacket (id_router_001_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_001_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_001_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),   //          .endofpacket
		.src1_ready         (rsp_xbar_demux_001_src1_ready),         //      src1.ready
		.src1_valid         (rsp_xbar_demux_001_src1_valid),         //          .valid
		.src1_data          (rsp_xbar_demux_001_src1_data),          //          .data
		.src1_channel       (rsp_xbar_demux_001_src1_channel),       //          .channel
		.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_demux_002 rsp_xbar_demux_002 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (width_adapter_001_src_ready),           //      sink.ready
		.sink_channel       (width_adapter_001_src_channel),         //          .channel
		.sink_data          (width_adapter_001_src_data),            //          .data
		.sink_startofpacket (width_adapter_001_src_startofpacket),   //          .startofpacket
		.sink_endofpacket   (width_adapter_001_src_endofpacket),     //          .endofpacket
		.sink_valid         (width_adapter_001_src_valid),           //          .valid
		.src0_ready         (rsp_xbar_demux_002_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_002_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_002_src0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_demux_002 rsp_xbar_demux_003 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (width_adapter_003_src_ready),           //      sink.ready
		.sink_channel       (width_adapter_003_src_channel),         //          .channel
		.sink_data          (width_adapter_003_src_data),            //          .data
		.sink_startofpacket (width_adapter_003_src_startofpacket),   //          .startofpacket
		.sink_endofpacket   (width_adapter_003_src_endofpacket),     //          .endofpacket
		.sink_valid         (width_adapter_003_src_valid),           //          .valid
		.src0_ready         (rsp_xbar_demux_003_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_003_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_003_src0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_reset_out_reset),         // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                 //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                 //          .valid
		.src_data            (rsp_xbar_mux_src_data),                  //          .data
		.src_channel         (rsp_xbar_mux_src_channel),               //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),         //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),           //          .endofpacket
		.sink0_ready         (mux_pipeline_007_source0_ready),         //     sink0.ready
		.sink0_valid         (mux_pipeline_007_source0_valid),         //          .valid
		.sink0_channel       (mux_pipeline_007_source0_channel),       //          .channel
		.sink0_data          (mux_pipeline_007_source0_data),          //          .data
		.sink0_startofpacket (mux_pipeline_007_source0_startofpacket), //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_007_source0_endofpacket),   //          .endofpacket
		.sink1_ready         (mux_pipeline_008_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_008_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_008_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_008_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_008_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_008_source0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_mux rsp_xbar_mux_001 (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_reset_out_reset),         // clk_reset.reset
		.src_ready           (rsp_xbar_mux_001_src_ready),             //       src.ready
		.src_valid           (rsp_xbar_mux_001_src_valid),             //          .valid
		.src_data            (rsp_xbar_mux_001_src_data),              //          .data
		.src_channel         (rsp_xbar_mux_001_src_channel),           //          .channel
		.src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),     //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),       //          .endofpacket
		.sink0_ready         (mux_pipeline_009_source0_ready),         //     sink0.ready
		.sink0_valid         (mux_pipeline_009_source0_valid),         //          .valid
		.sink0_channel       (mux_pipeline_009_source0_channel),       //          .channel
		.sink0_data          (mux_pipeline_009_source0_data),          //          .data
		.sink0_startofpacket (mux_pipeline_009_source0_startofpacket), //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_009_source0_endofpacket),   //          .endofpacket
		.sink1_ready         (mux_pipeline_010_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_010_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_010_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_010_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_010_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_010_source0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_mux_002 rsp_xbar_mux_002 (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_001_reset_out_reset),     // clk_reset.reset
		.src_ready           (rsp_xbar_mux_002_src_ready),             //       src.ready
		.src_valid           (rsp_xbar_mux_002_src_valid),             //          .valid
		.src_data            (rsp_xbar_mux_002_src_data),              //          .data
		.src_channel         (rsp_xbar_mux_002_src_channel),           //          .channel
		.src_startofpacket   (rsp_xbar_mux_002_src_startofpacket),     //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_002_src_endofpacket),       //          .endofpacket
		.sink0_ready         (mux_pipeline_011_source0_ready),         //     sink0.ready
		.sink0_valid         (mux_pipeline_011_source0_valid),         //          .valid
		.sink0_channel       (mux_pipeline_011_source0_channel),       //          .channel
		.sink0_data          (mux_pipeline_011_source0_data),          //          .data
		.sink0_startofpacket (mux_pipeline_011_source0_startofpacket), //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_011_source0_endofpacket),   //          .endofpacket
		.sink1_ready         (mux_pipeline_012_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_012_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_012_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_012_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_012_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_012_source0_endofpacket),   //          .endofpacket
		.sink2_ready         (mux_pipeline_013_source0_ready),         //     sink2.ready
		.sink2_valid         (mux_pipeline_013_source0_valid),         //          .valid
		.sink2_channel       (mux_pipeline_013_source0_channel),       //          .channel
		.sink2_data          (mux_pipeline_013_source0_data),          //          .data
		.sink2_startofpacket (mux_pipeline_013_source0_startofpacket), //          .startofpacket
		.sink2_endofpacket   (mux_pipeline_013_source0_endofpacket)    //          .endofpacket
	);

	q_sys_cmd_xbar_demux_003 cmd_xbar_demux_003 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),           //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),         // clk_reset.reset
		.sink_ready         (limiter_pipeline_004_source0_ready),         //      sink.ready
		.sink_channel       (limiter_pipeline_004_source0_channel),       //          .channel
		.sink_data          (limiter_pipeline_004_source0_data),          //          .data
		.sink_startofpacket (limiter_pipeline_004_source0_startofpacket), //          .startofpacket
		.sink_endofpacket   (limiter_pipeline_004_source0_endofpacket),   //          .endofpacket
		.sink_valid         (limiter_pipeline_004_source0_valid),         //          .valid
		.src0_ready         (cmd_xbar_demux_003_src0_ready),              //      src0.ready
		.src0_valid         (cmd_xbar_demux_003_src0_valid),              //          .valid
		.src0_data          (cmd_xbar_demux_003_src0_data),               //          .data
		.src0_channel       (cmd_xbar_demux_003_src0_channel),            //          .channel
		.src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket),      //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_003_src0_endofpacket),        //          .endofpacket
		.src1_ready         (cmd_xbar_demux_003_src1_ready),              //      src1.ready
		.src1_valid         (cmd_xbar_demux_003_src1_valid),              //          .valid
		.src1_data          (cmd_xbar_demux_003_src1_data),               //          .data
		.src1_channel       (cmd_xbar_demux_003_src1_channel),            //          .channel
		.src1_startofpacket (cmd_xbar_demux_003_src1_startofpacket),      //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_003_src1_endofpacket),        //          .endofpacket
		.src2_ready         (cmd_xbar_demux_003_src2_ready),              //      src2.ready
		.src2_valid         (cmd_xbar_demux_003_src2_valid),              //          .valid
		.src2_data          (cmd_xbar_demux_003_src2_data),               //          .data
		.src2_channel       (cmd_xbar_demux_003_src2_channel),            //          .channel
		.src2_startofpacket (cmd_xbar_demux_003_src2_startofpacket),      //          .startofpacket
		.src2_endofpacket   (cmd_xbar_demux_003_src2_endofpacket)         //          .endofpacket
	);

	q_sys_rsp_xbar_demux_004 rsp_xbar_demux_004 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),    // clk_reset.reset
		.sink_ready         (width_adapter_005_src_ready),           //      sink.ready
		.sink_channel       (width_adapter_005_src_channel),         //          .channel
		.sink_data          (width_adapter_005_src_data),            //          .data
		.sink_startofpacket (width_adapter_005_src_startofpacket),   //          .startofpacket
		.sink_endofpacket   (width_adapter_005_src_endofpacket),     //          .endofpacket
		.sink_valid         (width_adapter_005_src_valid),           //          .valid
		.src0_ready         (rsp_xbar_demux_004_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_004_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_004_src0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_demux_004 rsp_xbar_demux_005 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (width_adapter_007_src_ready),           //      sink.ready
		.sink_channel       (width_adapter_007_src_channel),         //          .channel
		.sink_data          (width_adapter_007_src_data),            //          .data
		.sink_startofpacket (width_adapter_007_src_startofpacket),   //          .startofpacket
		.sink_endofpacket   (width_adapter_007_src_endofpacket),     //          .endofpacket
		.sink_valid         (width_adapter_007_src_valid),           //          .valid
		.src0_ready         (rsp_xbar_demux_005_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_005_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_demux_004 rsp_xbar_demux_006 (
		.clk                (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (width_adapter_009_src_ready),           //      sink.ready
		.sink_channel       (width_adapter_009_src_channel),         //          .channel
		.sink_data          (width_adapter_009_src_data),            //          .data
		.sink_startofpacket (width_adapter_009_src_startofpacket),   //          .startofpacket
		.sink_endofpacket   (width_adapter_009_src_endofpacket),     //          .endofpacket
		.sink_valid         (width_adapter_009_src_valid),           //          .valid
		.src0_ready         (rsp_xbar_demux_006_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_006_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_006_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_006_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_006_src0_endofpacket)    //          .endofpacket
	);

	q_sys_rsp_xbar_mux_003 rsp_xbar_mux_003 (
		.clk                 (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset               (rst_controller_001_reset_out_reset),     // clk_reset.reset
		.src_ready           (rsp_xbar_mux_003_src_ready),             //       src.ready
		.src_valid           (rsp_xbar_mux_003_src_valid),             //          .valid
		.src_data            (rsp_xbar_mux_003_src_data),              //          .data
		.src_channel         (rsp_xbar_mux_003_src_channel),           //          .channel
		.src_startofpacket   (rsp_xbar_mux_003_src_startofpacket),     //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_003_src_endofpacket),       //          .endofpacket
		.sink0_ready         (mux_pipeline_017_source0_ready),         //     sink0.ready
		.sink0_valid         (mux_pipeline_017_source0_valid),         //          .valid
		.sink0_channel       (mux_pipeline_017_source0_channel),       //          .channel
		.sink0_data          (mux_pipeline_017_source0_data),          //          .data
		.sink0_startofpacket (mux_pipeline_017_source0_startofpacket), //          .startofpacket
		.sink0_endofpacket   (mux_pipeline_017_source0_endofpacket),   //          .endofpacket
		.sink1_ready         (mux_pipeline_018_source0_ready),         //     sink1.ready
		.sink1_valid         (mux_pipeline_018_source0_valid),         //          .valid
		.sink1_channel       (mux_pipeline_018_source0_channel),       //          .channel
		.sink1_data          (mux_pipeline_018_source0_data),          //          .data
		.sink1_startofpacket (mux_pipeline_018_source0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (mux_pipeline_018_source0_endofpacket),   //          .endofpacket
		.sink2_ready         (mux_pipeline_019_source0_ready),         //     sink2.ready
		.sink2_valid         (mux_pipeline_019_source0_valid),         //          .valid
		.sink2_channel       (mux_pipeline_019_source0_channel),       //          .channel
		.sink2_data          (mux_pipeline_019_source0_data),          //          .data
		.sink2_startofpacket (mux_pipeline_019_source0_startofpacket), //          .startofpacket
		.sink2_endofpacket   (mux_pipeline_019_source0_endofpacket)    //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (152),
		.IN_PKT_RESPONSE_STATUS_L      (151),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_ST_DATA_W                  (153),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (96),
		.OUT_PKT_BURST_SIZE_L          (94),
		.OUT_PKT_RESPONSE_STATUS_H     (116),
		.OUT_PKT_RESPONSE_STATUS_L     (115),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (98),
		.OUT_PKT_BURST_TYPE_L          (97),
		.OUT_ST_DATA_W                 (117),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset                (rst_controller_reset_out_reset),         // clk_reset.reset
		.in_valid             (mux_pipeline_005_source0_valid),         //      sink.valid
		.in_channel           (mux_pipeline_005_source0_channel),       //          .channel
		.in_startofpacket     (mux_pipeline_005_source0_startofpacket), //          .startofpacket
		.in_endofpacket       (mux_pipeline_005_source0_endofpacket),   //          .endofpacket
		.in_ready             (mux_pipeline_005_source0_ready),         //          .ready
		.in_data              (mux_pipeline_005_source0_data),          //          .data
		.out_endofpacket      (width_adapter_src_endofpacket),          //       src.endofpacket
		.out_data             (width_adapter_src_data),                 //          .data
		.out_channel          (width_adapter_src_channel),              //          .channel
		.out_valid            (width_adapter_src_valid),                //          .valid
		.out_ready            (width_adapter_src_ready),                //          .ready
		.out_startofpacket    (width_adapter_src_startofpacket),        //          .startofpacket
		.in_command_size_data (3'b000)                                  // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (93),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (96),
		.IN_PKT_BURST_SIZE_L           (94),
		.IN_PKT_RESPONSE_STATUS_H      (116),
		.IN_PKT_RESPONSE_STATUS_L      (115),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (98),
		.IN_PKT_BURST_TYPE_L           (97),
		.IN_ST_DATA_W                  (117),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (152),
		.OUT_PKT_RESPONSE_STATUS_L     (151),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_ST_DATA_W                 (153),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_001 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),    //       clk.clk
		.reset                (rst_controller_reset_out_reset),      // clk_reset.reset
		.in_valid             (id_router_002_src_valid),             //      sink.valid
		.in_channel           (id_router_002_src_channel),           //          .channel
		.in_startofpacket     (id_router_002_src_startofpacket),     //          .startofpacket
		.in_endofpacket       (id_router_002_src_endofpacket),       //          .endofpacket
		.in_ready             (id_router_002_src_ready),             //          .ready
		.in_data              (id_router_002_src_data),              //          .data
		.out_endofpacket      (width_adapter_001_src_endofpacket),   //       src.endofpacket
		.out_data             (width_adapter_001_src_data),          //          .data
		.out_channel          (width_adapter_001_src_channel),       //          .channel
		.out_valid            (width_adapter_001_src_valid),         //          .valid
		.out_ready            (width_adapter_001_src_ready),         //          .ready
		.out_startofpacket    (width_adapter_001_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                               // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (152),
		.IN_PKT_RESPONSE_STATUS_L      (151),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_ST_DATA_W                  (153),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (96),
		.OUT_PKT_BURST_SIZE_L          (94),
		.OUT_PKT_RESPONSE_STATUS_H     (116),
		.OUT_PKT_RESPONSE_STATUS_L     (115),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (98),
		.OUT_PKT_BURST_TYPE_L          (97),
		.OUT_ST_DATA_W                 (117),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_002 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset                (rst_controller_reset_out_reset),         // clk_reset.reset
		.in_valid             (mux_pipeline_006_source0_valid),         //      sink.valid
		.in_channel           (mux_pipeline_006_source0_channel),       //          .channel
		.in_startofpacket     (mux_pipeline_006_source0_startofpacket), //          .startofpacket
		.in_endofpacket       (mux_pipeline_006_source0_endofpacket),   //          .endofpacket
		.in_ready             (mux_pipeline_006_source0_ready),         //          .ready
		.in_data              (mux_pipeline_006_source0_data),          //          .data
		.out_endofpacket      (width_adapter_002_src_endofpacket),      //       src.endofpacket
		.out_data             (width_adapter_002_src_data),             //          .data
		.out_channel          (width_adapter_002_src_channel),          //          .channel
		.out_valid            (width_adapter_002_src_valid),            //          .valid
		.out_ready            (width_adapter_002_src_ready),            //          .ready
		.out_startofpacket    (width_adapter_002_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                  // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (93),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (96),
		.IN_PKT_BURST_SIZE_L           (94),
		.IN_PKT_RESPONSE_STATUS_H      (116),
		.IN_PKT_RESPONSE_STATUS_L      (115),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (98),
		.IN_PKT_BURST_TYPE_L           (97),
		.IN_ST_DATA_W                  (117),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (152),
		.OUT_PKT_RESPONSE_STATUS_L     (151),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_ST_DATA_W                 (153),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_003 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),    //       clk.clk
		.reset                (rst_controller_reset_out_reset),      // clk_reset.reset
		.in_valid             (id_router_003_src_valid),             //      sink.valid
		.in_channel           (id_router_003_src_channel),           //          .channel
		.in_startofpacket     (id_router_003_src_startofpacket),     //          .startofpacket
		.in_endofpacket       (id_router_003_src_endofpacket),       //          .endofpacket
		.in_ready             (id_router_003_src_ready),             //          .ready
		.in_data              (id_router_003_src_data),              //          .data
		.out_endofpacket      (width_adapter_003_src_endofpacket),   //       src.endofpacket
		.out_data             (width_adapter_003_src_data),          //          .data
		.out_channel          (width_adapter_003_src_channel),       //          .channel
		.out_valid            (width_adapter_003_src_valid),         //          .valid
		.out_ready            (width_adapter_003_src_ready),         //          .ready
		.out_startofpacket    (width_adapter_003_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                               // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (152),
		.IN_PKT_RESPONSE_STATUS_L      (151),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_ST_DATA_W                  (153),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (96),
		.OUT_PKT_BURST_SIZE_L          (94),
		.OUT_PKT_RESPONSE_STATUS_H     (116),
		.OUT_PKT_RESPONSE_STATUS_L     (115),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (98),
		.OUT_PKT_BURST_TYPE_L          (97),
		.OUT_ST_DATA_W                 (117),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_004 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset                (rst_controller_001_reset_out_reset),     // clk_reset.reset
		.in_valid             (mux_pipeline_014_source0_valid),         //      sink.valid
		.in_channel           (mux_pipeline_014_source0_channel),       //          .channel
		.in_startofpacket     (mux_pipeline_014_source0_startofpacket), //          .startofpacket
		.in_endofpacket       (mux_pipeline_014_source0_endofpacket),   //          .endofpacket
		.in_ready             (mux_pipeline_014_source0_ready),         //          .ready
		.in_data              (mux_pipeline_014_source0_data),          //          .data
		.out_endofpacket      (width_adapter_004_src_endofpacket),      //       src.endofpacket
		.out_data             (width_adapter_004_src_data),             //          .data
		.out_channel          (width_adapter_004_src_channel),          //          .channel
		.out_valid            (width_adapter_004_src_valid),            //          .valid
		.out_ready            (width_adapter_004_src_ready),            //          .ready
		.out_startofpacket    (width_adapter_004_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                  // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (93),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (96),
		.IN_PKT_BURST_SIZE_L           (94),
		.IN_PKT_RESPONSE_STATUS_H      (116),
		.IN_PKT_RESPONSE_STATUS_L      (115),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (98),
		.IN_PKT_BURST_TYPE_L           (97),
		.IN_ST_DATA_W                  (117),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (152),
		.OUT_PKT_RESPONSE_STATUS_L     (151),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_ST_DATA_W                 (153),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_005 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),    //       clk.clk
		.reset                (rst_controller_001_reset_out_reset),  // clk_reset.reset
		.in_valid             (id_router_004_src_valid),             //      sink.valid
		.in_channel           (id_router_004_src_channel),           //          .channel
		.in_startofpacket     (id_router_004_src_startofpacket),     //          .startofpacket
		.in_endofpacket       (id_router_004_src_endofpacket),       //          .endofpacket
		.in_ready             (id_router_004_src_ready),             //          .ready
		.in_data              (id_router_004_src_data),              //          .data
		.out_endofpacket      (width_adapter_005_src_endofpacket),   //       src.endofpacket
		.out_data             (width_adapter_005_src_data),          //          .data
		.out_channel          (width_adapter_005_src_channel),       //          .channel
		.out_valid            (width_adapter_005_src_valid),         //          .valid
		.out_ready            (width_adapter_005_src_ready),         //          .ready
		.out_startofpacket    (width_adapter_005_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                               // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (152),
		.IN_PKT_RESPONSE_STATUS_L      (151),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_ST_DATA_W                  (153),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (96),
		.OUT_PKT_BURST_SIZE_L          (94),
		.OUT_PKT_RESPONSE_STATUS_H     (116),
		.OUT_PKT_RESPONSE_STATUS_L     (115),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (98),
		.OUT_PKT_BURST_TYPE_L          (97),
		.OUT_ST_DATA_W                 (117),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_006 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset                (rst_controller_reset_out_reset),         // clk_reset.reset
		.in_valid             (mux_pipeline_015_source0_valid),         //      sink.valid
		.in_channel           (mux_pipeline_015_source0_channel),       //          .channel
		.in_startofpacket     (mux_pipeline_015_source0_startofpacket), //          .startofpacket
		.in_endofpacket       (mux_pipeline_015_source0_endofpacket),   //          .endofpacket
		.in_ready             (mux_pipeline_015_source0_ready),         //          .ready
		.in_data              (mux_pipeline_015_source0_data),          //          .data
		.out_endofpacket      (width_adapter_006_src_endofpacket),      //       src.endofpacket
		.out_data             (width_adapter_006_src_data),             //          .data
		.out_channel          (width_adapter_006_src_channel),          //          .channel
		.out_valid            (width_adapter_006_src_valid),            //          .valid
		.out_ready            (width_adapter_006_src_ready),            //          .ready
		.out_startofpacket    (width_adapter_006_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                  // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (93),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (96),
		.IN_PKT_BURST_SIZE_L           (94),
		.IN_PKT_RESPONSE_STATUS_H      (116),
		.IN_PKT_RESPONSE_STATUS_L      (115),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (98),
		.IN_PKT_BURST_TYPE_L           (97),
		.IN_ST_DATA_W                  (117),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (152),
		.OUT_PKT_RESPONSE_STATUS_L     (151),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_ST_DATA_W                 (153),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_007 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),    //       clk.clk
		.reset                (rst_controller_reset_out_reset),      // clk_reset.reset
		.in_valid             (id_router_005_src_valid),             //      sink.valid
		.in_channel           (id_router_005_src_channel),           //          .channel
		.in_startofpacket     (id_router_005_src_startofpacket),     //          .startofpacket
		.in_endofpacket       (id_router_005_src_endofpacket),       //          .endofpacket
		.in_ready             (id_router_005_src_ready),             //          .ready
		.in_data              (id_router_005_src_data),              //          .data
		.out_endofpacket      (width_adapter_007_src_endofpacket),   //       src.endofpacket
		.out_data             (width_adapter_007_src_data),          //          .data
		.out_channel          (width_adapter_007_src_channel),       //          .channel
		.out_valid            (width_adapter_007_src_valid),         //          .valid
		.out_ready            (width_adapter_007_src_ready),         //          .ready
		.out_startofpacket    (width_adapter_007_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                               // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (152),
		.IN_PKT_RESPONSE_STATUS_L      (151),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_ST_DATA_W                  (153),
		.OUT_PKT_ADDR_H                (175),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (191),
		.OUT_PKT_BYTE_CNT_L            (182),
		.OUT_PKT_TRANS_COMPRESSED_READ (176),
		.OUT_PKT_BURST_SIZE_H          (204),
		.OUT_PKT_BURST_SIZE_L          (202),
		.OUT_PKT_RESPONSE_STATUS_H     (224),
		.OUT_PKT_RESPONSE_STATUS_L     (223),
		.OUT_PKT_TRANS_EXCLUSIVE       (181),
		.OUT_PKT_BURST_TYPE_H          (206),
		.OUT_PKT_BURST_TYPE_L          (205),
		.OUT_ST_DATA_W                 (225),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_008 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),       //       clk.clk
		.reset                (rst_controller_reset_out_reset),         // clk_reset.reset
		.in_valid             (mux_pipeline_016_source0_valid),         //      sink.valid
		.in_channel           (mux_pipeline_016_source0_channel),       //          .channel
		.in_startofpacket     (mux_pipeline_016_source0_startofpacket), //          .startofpacket
		.in_endofpacket       (mux_pipeline_016_source0_endofpacket),   //          .endofpacket
		.in_ready             (mux_pipeline_016_source0_ready),         //          .ready
		.in_data              (mux_pipeline_016_source0_data),          //          .data
		.out_endofpacket      (width_adapter_008_src_endofpacket),      //       src.endofpacket
		.out_data             (width_adapter_008_src_data),             //          .data
		.out_channel          (width_adapter_008_src_channel),          //          .channel
		.out_valid            (width_adapter_008_src_valid),            //          .valid
		.out_ready            (width_adapter_008_src_ready),            //          .ready
		.out_startofpacket    (width_adapter_008_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                  // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (175),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (191),
		.IN_PKT_BYTE_CNT_L             (182),
		.IN_PKT_TRANS_COMPRESSED_READ  (176),
		.IN_PKT_BURSTWRAP_H            (201),
		.IN_PKT_BURSTWRAP_L            (192),
		.IN_PKT_BURST_SIZE_H           (204),
		.IN_PKT_BURST_SIZE_L           (202),
		.IN_PKT_RESPONSE_STATUS_H      (224),
		.IN_PKT_RESPONSE_STATUS_L      (223),
		.IN_PKT_TRANS_EXCLUSIVE        (181),
		.IN_PKT_BURST_TYPE_H           (206),
		.IN_PKT_BURST_TYPE_L           (205),
		.IN_ST_DATA_W                  (225),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (152),
		.OUT_PKT_RESPONSE_STATUS_L     (151),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_ST_DATA_W                 (153),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_009 (
		.clk                  (pcie_hard_ip_0_pcie_core_clk_clk),    //       clk.clk
		.reset                (rst_controller_reset_out_reset),      // clk_reset.reset
		.in_valid             (id_router_006_src_valid),             //      sink.valid
		.in_channel           (id_router_006_src_channel),           //          .channel
		.in_startofpacket     (id_router_006_src_startofpacket),     //          .startofpacket
		.in_endofpacket       (id_router_006_src_endofpacket),       //          .endofpacket
		.in_ready             (id_router_006_src_ready),             //          .ready
		.in_data              (id_router_006_src_data),              //          .data
		.out_endofpacket      (width_adapter_009_src_endofpacket),   //       src.endofpacket
		.out_data             (width_adapter_009_src_data),          //          .data
		.out_channel          (width_adapter_009_src_channel),       //          .channel
		.out_valid            (width_adapter_009_src_valid),         //          .valid
		.out_ready            (width_adapter_009_src_ready),         //          .ready
		.out_startofpacket    (width_adapter_009_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                               // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (limiter_cmd_src_ready),                  //     sink0.ready
		.in_valid          (limiter_cmd_src_valid),                  //          .valid
		.in_startofpacket  (limiter_cmd_src_startofpacket),          //          .startofpacket
		.in_endofpacket    (limiter_cmd_src_endofpacket),            //          .endofpacket
		.in_data           (limiter_cmd_src_data),                   //          .data
		.in_channel        (limiter_cmd_src_channel),                //          .channel
		.out_ready         (limiter_pipeline_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_source0_data),          //          .data
		.out_channel       (limiter_pipeline_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_001 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),           //       cr0.clk
		.reset             (rst_controller_reset_out_reset),             // cr0_reset.reset
		.in_ready          (rsp_xbar_mux_001_src_ready),                 //     sink0.ready
		.in_valid          (rsp_xbar_mux_001_src_valid),                 //          .valid
		.in_startofpacket  (rsp_xbar_mux_001_src_startofpacket),         //          .startofpacket
		.in_endofpacket    (rsp_xbar_mux_001_src_endofpacket),           //          .endofpacket
		.in_data           (rsp_xbar_mux_001_src_data),                  //          .data
		.in_channel        (rsp_xbar_mux_001_src_channel),               //          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),          //          .data
		.out_channel       (limiter_pipeline_001_source0_channel),       //          .channel
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.out_error         (),                                           // (terminated)
		.in_error          (1'b0)                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_002 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),           //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),         // cr0_reset.reset
		.in_ready          (limiter_001_cmd_src_ready),                  //     sink0.ready
		.in_valid          (limiter_001_cmd_src_valid),                  //          .valid
		.in_startofpacket  (limiter_001_cmd_src_startofpacket),          //          .startofpacket
		.in_endofpacket    (limiter_001_cmd_src_endofpacket),            //          .endofpacket
		.in_data           (limiter_001_cmd_src_data),                   //          .data
		.in_channel        (limiter_001_cmd_src_channel),                //          .channel
		.out_ready         (limiter_pipeline_002_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_002_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_002_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_002_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_002_source0_data),          //          .data
		.out_channel       (limiter_pipeline_002_source0_channel),       //          .channel
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.out_error         (),                                           // (terminated)
		.in_error          (1'b0)                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_003 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),           //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_mux_002_src_ready),                 //     sink0.ready
		.in_valid          (rsp_xbar_mux_002_src_valid),                 //          .valid
		.in_startofpacket  (rsp_xbar_mux_002_src_startofpacket),         //          .startofpacket
		.in_endofpacket    (rsp_xbar_mux_002_src_endofpacket),           //          .endofpacket
		.in_data           (rsp_xbar_mux_002_src_data),                  //          .data
		.in_channel        (rsp_xbar_mux_002_src_channel),               //          .channel
		.out_ready         (limiter_pipeline_003_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_003_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_003_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_003_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_003_source0_data),          //          .data
		.out_channel       (limiter_pipeline_003_source0_channel),       //          .channel
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.out_error         (),                                           // (terminated)
		.in_error          (1'b0)                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_004 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),           //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),         // cr0_reset.reset
		.in_ready          (limiter_002_cmd_src_ready),                  //     sink0.ready
		.in_valid          (limiter_002_cmd_src_valid),                  //          .valid
		.in_startofpacket  (limiter_002_cmd_src_startofpacket),          //          .startofpacket
		.in_endofpacket    (limiter_002_cmd_src_endofpacket),            //          .endofpacket
		.in_data           (limiter_002_cmd_src_data),                   //          .data
		.in_channel        (limiter_002_cmd_src_channel),                //          .channel
		.out_ready         (limiter_pipeline_004_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_004_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_004_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_004_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_004_source0_data),          //          .data
		.out_channel       (limiter_pipeline_004_source0_channel),       //          .channel
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.out_error         (),                                           // (terminated)
		.in_error          (1'b0)                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_005 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),           //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_mux_003_src_ready),                 //     sink0.ready
		.in_valid          (rsp_xbar_mux_003_src_valid),                 //          .valid
		.in_startofpacket  (rsp_xbar_mux_003_src_startofpacket),         //          .startofpacket
		.in_endofpacket    (rsp_xbar_mux_003_src_endofpacket),           //          .endofpacket
		.in_data           (rsp_xbar_mux_003_src_data),                  //          .data
		.in_channel        (rsp_xbar_mux_003_src_channel),               //          .channel
		.out_ready         (limiter_pipeline_005_source0_ready),         //   source0.ready
		.out_valid         (limiter_pipeline_005_source0_valid),         //          .valid
		.out_startofpacket (limiter_pipeline_005_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (limiter_pipeline_005_source0_endofpacket),   //          .endofpacket
		.out_data          (limiter_pipeline_005_source0_data),          //          .data
		.out_channel       (limiter_pipeline_005_source0_channel),       //          .channel
		.in_empty          (1'b0),                                       // (terminated)
		.out_empty         (),                                           // (terminated)
		.out_error         (),                                           // (terminated)
		.in_error          (1'b0)                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),     //       cr0.clk
		.reset             (rst_controller_reset_out_reset),       // cr0_reset.reset
		.in_ready          (burst_adapter_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_source0_data),           //          .data
		.in_channel        (burst_adapter_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_source0_data),          //          .data
		.out_channel       (agent_pipeline_source0_channel),       //          .channel
		.in_empty          (1'b0),                                 // (terminated)
		.out_empty         (),                                     // (terminated)
		.out_error         (),                                     // (terminated)
		.in_error          (1'b0)                                  // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_001 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                               //       cr0.clk
		.reset             (rst_controller_reset_out_reset),                                                 // cr0_reset.reset
		.in_ready          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_001_source0_ready),                                               //   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                                               //          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                                       //          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                                         //          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                                //          .data
		.in_empty          (1'b0),                                                                           // (terminated)
		.out_empty         (),                                                                               // (terminated)
		.out_error         (),                                                                               // (terminated)
		.in_error          (1'b0),                                                                           // (terminated)
		.out_channel       (),                                                                               // (terminated)
		.in_channel        (1'b0)                                                                            // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_002 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),       // cr0_reset.reset
		.in_ready          (cmd_xbar_mux_001_src_ready),               //     sink0.ready
		.in_valid          (cmd_xbar_mux_001_src_valid),               //          .valid
		.in_startofpacket  (cmd_xbar_mux_001_src_startofpacket),       //          .startofpacket
		.in_endofpacket    (cmd_xbar_mux_001_src_endofpacket),         //          .endofpacket
		.in_data           (cmd_xbar_mux_001_src_data),                //          .data
		.in_channel        (cmd_xbar_mux_001_src_channel),             //          .channel
		.out_ready         (agent_pipeline_002_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),          //          .data
		.out_channel       (agent_pipeline_002_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_003 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                              //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),                                            // cr0_reset.reset
		.in_ready          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (pcie_hard_ip_0_txs_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_003_source0_ready),                                              //   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),                                              //          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),                                      //          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),                                        //          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),                                               //          .data
		.in_empty          (1'b0),                                                                          // (terminated)
		.out_empty         (),                                                                              // (terminated)
		.out_error         (),                                                                              // (terminated)
		.in_error          (1'b0),                                                                          // (terminated)
		.out_channel       (),                                                                              // (terminated)
		.in_channel        (1'b0)                                                                           // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_004 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_reset_out_reset),           // cr0_reset.reset
		.in_ready          (burst_adapter_001_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_001_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_001_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_001_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_001_source0_data),           //          .data
		.in_channel        (burst_adapter_001_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_004_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_004_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_004_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_004_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_004_source0_data),          //          .data
		.out_channel       (agent_pipeline_004_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_005 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                      //       cr0.clk
		.reset             (rst_controller_reset_out_reset),                                        // cr0_reset.reset
		.in_ready          (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_005_source0_ready),                                      //   source0.ready
		.out_valid         (agent_pipeline_005_source0_valid),                                      //          .valid
		.out_startofpacket (agent_pipeline_005_source0_startofpacket),                              //          .startofpacket
		.out_endofpacket   (agent_pipeline_005_source0_endofpacket),                                //          .endofpacket
		.out_data          (agent_pipeline_005_source0_data),                                       //          .data
		.in_empty          (1'b0),                                                                  // (terminated)
		.out_empty         (),                                                                      // (terminated)
		.out_error         (),                                                                      // (terminated)
		.in_error          (1'b0),                                                                  // (terminated)
		.out_channel       (),                                                                      // (terminated)
		.in_channel        (1'b0)                                                                   // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_006 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_reset_out_reset),           // cr0_reset.reset
		.in_ready          (burst_adapter_002_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_002_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_002_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_002_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_002_source0_data),           //          .data
		.in_channel        (burst_adapter_002_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_006_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_006_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_006_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_006_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_006_source0_data),          //          .data
		.out_channel       (agent_pipeline_006_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_007 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                     //       cr0.clk
		.reset             (rst_controller_reset_out_reset),                                       // cr0_reset.reset
		.in_ready          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (pio_pb_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_007_source0_ready),                                     //   source0.ready
		.out_valid         (agent_pipeline_007_source0_valid),                                     //          .valid
		.out_startofpacket (agent_pipeline_007_source0_startofpacket),                             //          .startofpacket
		.out_endofpacket   (agent_pipeline_007_source0_endofpacket),                               //          .endofpacket
		.out_data          (agent_pipeline_007_source0_data),                                      //          .data
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_error          (1'b0),                                                                 // (terminated)
		.out_channel       (),                                                                     // (terminated)
		.in_channel        (1'b0)                                                                  // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_008 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),       // cr0_reset.reset
		.in_ready          (burst_adapter_003_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_003_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_003_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_003_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_003_source0_data),           //          .data
		.in_channel        (burst_adapter_003_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_008_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_008_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_008_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_008_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_008_source0_data),          //          .data
		.out_channel       (agent_pipeline_008_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_009 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                              //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),                                            // cr0_reset.reset
		.in_ready          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (pcie_hard_ip_0_cra_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_009_source0_ready),                                              //   source0.ready
		.out_valid         (agent_pipeline_009_source0_valid),                                              //          .valid
		.out_startofpacket (agent_pipeline_009_source0_startofpacket),                                      //          .startofpacket
		.out_endofpacket   (agent_pipeline_009_source0_endofpacket),                                        //          .endofpacket
		.out_data          (agent_pipeline_009_source0_data),                                               //          .data
		.in_empty          (1'b0),                                                                          // (terminated)
		.out_empty         (),                                                                              // (terminated)
		.out_error         (),                                                                              // (terminated)
		.in_error          (1'b0),                                                                          // (terminated)
		.out_channel       (),                                                                              // (terminated)
		.in_channel        (1'b0)                                                                           // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_010 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_reset_out_reset),           // cr0_reset.reset
		.in_ready          (burst_adapter_004_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_004_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_004_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_004_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_004_source0_data),           //          .data
		.in_channel        (burst_adapter_004_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_010_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_010_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_010_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_010_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_010_source0_data),          //          .data
		.out_channel       (agent_pipeline_010_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (117),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_011 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                          //       cr0.clk
		.reset             (rst_controller_reset_out_reset),                                                            // cr0_reset.reset
		.in_ready          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (modular_sgdma_dispatcher_0_csr_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_011_source0_ready),                                                          //   source0.ready
		.out_valid         (agent_pipeline_011_source0_valid),                                                          //          .valid
		.out_startofpacket (agent_pipeline_011_source0_startofpacket),                                                  //          .startofpacket
		.out_endofpacket   (agent_pipeline_011_source0_endofpacket),                                                    //          .endofpacket
		.out_data          (agent_pipeline_011_source0_data),                                                           //          .data
		.in_empty          (1'b0),                                                                                      // (terminated)
		.out_empty         (),                                                                                          // (terminated)
		.out_error         (),                                                                                          // (terminated)
		.in_error          (1'b0),                                                                                      // (terminated)
		.out_channel       (),                                                                                          // (terminated)
		.in_channel        (1'b0)                                                                                       // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (225),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_012 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),         //       cr0.clk
		.reset             (rst_controller_reset_out_reset),           // cr0_reset.reset
		.in_ready          (burst_adapter_005_source0_ready),          //     sink0.ready
		.in_valid          (burst_adapter_005_source0_valid),          //          .valid
		.in_startofpacket  (burst_adapter_005_source0_startofpacket),  //          .startofpacket
		.in_endofpacket    (burst_adapter_005_source0_endofpacket),    //          .endofpacket
		.in_data           (burst_adapter_005_source0_data),           //          .data
		.in_channel        (burst_adapter_005_source0_channel),        //          .channel
		.out_ready         (agent_pipeline_012_source0_ready),         //   source0.ready
		.out_valid         (agent_pipeline_012_source0_valid),         //          .valid
		.out_startofpacket (agent_pipeline_012_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (agent_pipeline_012_source0_endofpacket),   //          .endofpacket
		.out_data          (agent_pipeline_012_source0_data),          //          .data
		.out_channel       (agent_pipeline_012_source0_channel),       //          .channel
		.in_empty          (1'b0),                                     // (terminated)
		.out_empty         (),                                         // (terminated)
		.out_error         (),                                         // (terminated)
		.in_error          (1'b0)                                      // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (225),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_013 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),                                                                       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),                                                                         // cr0_reset.reset
		.in_ready          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //     sink0.ready
		.in_valid          (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.in_startofpacket  (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (modular_sgdma_dispatcher_0_descriptor_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_013_source0_ready),                                                                       //   source0.ready
		.out_valid         (agent_pipeline_013_source0_valid),                                                                       //          .valid
		.out_startofpacket (agent_pipeline_013_source0_startofpacket),                                                               //          .startofpacket
		.out_endofpacket   (agent_pipeline_013_source0_endofpacket),                                                                 //          .endofpacket
		.out_data          (agent_pipeline_013_source0_data),                                                                        //          .data
		.in_empty          (1'b0),                                                                                                   // (terminated)
		.out_empty         (),                                                                                                       // (terminated)
		.out_error         (),                                                                                                       // (terminated)
		.in_error          (1'b0),                                                                                                   // (terminated)
		.out_channel       (),                                                                                                       // (terminated)
		.in_channel        (1'b0)                                                                                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),   //       cr0.clk
		.reset             (rst_controller_reset_out_reset),     // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_src0_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_src0_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src0_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_src0_data),           //          .data
		.in_channel        (cmd_xbar_demux_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_source0_data),          //          .data
		.out_channel       (mux_pipeline_source0_channel),       //          .channel
		.in_empty          (1'b0),                               // (terminated)
		.out_empty         (),                                   // (terminated)
		.out_error         (),                                   // (terminated)
		.in_error          (1'b0)                                // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_001 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_001_src0_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_001_src0_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_001_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src0_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_001_src0_data),           //          .data
		.in_channel        (cmd_xbar_demux_001_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_001_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_001_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_001_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_001_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_001_source0_data),          //          .data
		.out_channel       (mux_pipeline_001_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_002 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_002_src0_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_002_src0_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_002_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_002_src0_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_002_src0_data),           //          .data
		.in_channel        (cmd_xbar_demux_002_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_002_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_002_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_002_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_002_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_002_source0_data),          //          .data
		.out_channel       (mux_pipeline_002_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_003 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_src1_ready),              //     sink0.ready
		.in_valid          (cmd_xbar_demux_src1_valid),              //          .valid
		.in_startofpacket  (cmd_xbar_demux_src1_startofpacket),      //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src1_endofpacket),        //          .endofpacket
		.in_data           (cmd_xbar_demux_src1_data),               //          .data
		.in_channel        (cmd_xbar_demux_src1_channel),            //          .channel
		.out_ready         (mux_pipeline_003_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_003_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_003_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_003_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_003_source0_data),          //          .data
		.out_channel       (mux_pipeline_003_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_004 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_001_src1_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_001_src1_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_001_src1_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src1_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_001_src1_data),           //          .data
		.in_channel        (cmd_xbar_demux_001_src1_channel),        //          .channel
		.out_ready         (mux_pipeline_004_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_004_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_004_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_004_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_004_source0_data),          //          .data
		.out_channel       (mux_pipeline_004_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_005 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_002_src1_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_002_src1_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_002_src1_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_002_src1_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_002_src1_data),           //          .data
		.in_channel        (cmd_xbar_demux_002_src1_channel),        //          .channel
		.out_ready         (mux_pipeline_005_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_005_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_005_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_005_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_005_source0_data),          //          .data
		.out_channel       (mux_pipeline_005_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_006 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_002_src2_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_002_src2_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_002_src2_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_002_src2_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_002_src2_data),           //          .data
		.in_channel        (cmd_xbar_demux_002_src2_channel),        //          .channel
		.out_ready         (mux_pipeline_006_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_006_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_006_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_006_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_006_source0_data),          //          .data
		.out_channel       (mux_pipeline_006_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_007 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_src0_ready),              //     sink0.ready
		.in_valid          (rsp_xbar_demux_src0_valid),              //          .valid
		.in_startofpacket  (rsp_xbar_demux_src0_startofpacket),      //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src0_endofpacket),        //          .endofpacket
		.in_data           (rsp_xbar_demux_src0_data),               //          .data
		.in_channel        (rsp_xbar_demux_src0_channel),            //          .channel
		.out_ready         (mux_pipeline_007_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_007_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_007_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_007_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_007_source0_data),          //          .data
		.out_channel       (mux_pipeline_007_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_008 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_001_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_001_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_001_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_001_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_001_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_001_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_008_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_008_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_008_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_008_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_008_source0_data),          //          .data
		.out_channel       (mux_pipeline_008_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_009 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_src1_ready),              //     sink0.ready
		.in_valid          (rsp_xbar_demux_src1_valid),              //          .valid
		.in_startofpacket  (rsp_xbar_demux_src1_startofpacket),      //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src1_endofpacket),        //          .endofpacket
		.in_data           (rsp_xbar_demux_src1_data),               //          .data
		.in_channel        (rsp_xbar_demux_src1_channel),            //          .channel
		.out_ready         (mux_pipeline_009_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_009_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_009_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_009_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_009_source0_data),          //          .data
		.out_channel       (mux_pipeline_009_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_010 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_001_src1_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_001_src1_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_001_src1_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_001_src1_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_001_src1_data),           //          .data
		.in_channel        (rsp_xbar_demux_001_src1_channel),        //          .channel
		.out_ready         (mux_pipeline_010_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_010_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_010_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_010_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_010_source0_data),          //          .data
		.out_channel       (mux_pipeline_010_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_011 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_src2_ready),              //     sink0.ready
		.in_valid          (rsp_xbar_demux_src2_valid),              //          .valid
		.in_startofpacket  (rsp_xbar_demux_src2_startofpacket),      //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src2_endofpacket),        //          .endofpacket
		.in_data           (rsp_xbar_demux_src2_data),               //          .data
		.in_channel        (rsp_xbar_demux_src2_channel),            //          .channel
		.out_ready         (mux_pipeline_011_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_011_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_011_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_011_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_011_source0_data),          //          .data
		.out_channel       (mux_pipeline_011_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_012 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_002_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_002_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_002_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_002_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_002_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_002_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_012_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_012_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_012_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_012_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_012_source0_data),          //          .data
		.out_channel       (mux_pipeline_012_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_013 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_003_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_003_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_003_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_003_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_003_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_003_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_013_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_013_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_013_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_013_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_013_source0_data),          //          .data
		.out_channel       (mux_pipeline_013_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_014 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_003_src0_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_003_src0_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_003_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_003_src0_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_003_src0_data),           //          .data
		.in_channel        (cmd_xbar_demux_003_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_014_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_014_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_014_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_014_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_014_source0_data),          //          .data
		.out_channel       (mux_pipeline_014_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_015 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_003_src1_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_003_src1_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_003_src1_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_003_src1_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_003_src1_data),           //          .data
		.in_channel        (cmd_xbar_demux_003_src1_channel),        //          .channel
		.out_ready         (mux_pipeline_015_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_015_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_015_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_015_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_015_source0_data),          //          .data
		.out_channel       (mux_pipeline_015_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_016 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_reset_out_reset),         // cr0_reset.reset
		.in_ready          (cmd_xbar_demux_003_src2_ready),          //     sink0.ready
		.in_valid          (cmd_xbar_demux_003_src2_valid),          //          .valid
		.in_startofpacket  (cmd_xbar_demux_003_src2_startofpacket),  //          .startofpacket
		.in_endofpacket    (cmd_xbar_demux_003_src2_endofpacket),    //          .endofpacket
		.in_data           (cmd_xbar_demux_003_src2_data),           //          .data
		.in_channel        (cmd_xbar_demux_003_src2_channel),        //          .channel
		.out_ready         (mux_pipeline_016_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_016_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_016_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_016_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_016_source0_data),          //          .data
		.out_channel       (mux_pipeline_016_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_017 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_004_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_004_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_004_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_004_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_004_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_004_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_017_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_017_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_017_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_017_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_017_source0_data),          //          .data
		.out_channel       (mux_pipeline_017_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_018 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_005_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_005_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_005_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_005_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_005_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_005_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_018_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_018_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_018_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_018_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_018_source0_data),          //          .data
		.out_channel       (mux_pipeline_018_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (153),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (3),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) mux_pipeline_019 (
		.clk               (pcie_hard_ip_0_pcie_core_clk_clk),       //       cr0.clk
		.reset             (rst_controller_001_reset_out_reset),     // cr0_reset.reset
		.in_ready          (rsp_xbar_demux_006_src0_ready),          //     sink0.ready
		.in_valid          (rsp_xbar_demux_006_src0_valid),          //          .valid
		.in_startofpacket  (rsp_xbar_demux_006_src0_startofpacket),  //          .startofpacket
		.in_endofpacket    (rsp_xbar_demux_006_src0_endofpacket),    //          .endofpacket
		.in_data           (rsp_xbar_demux_006_src0_data),           //          .data
		.in_channel        (rsp_xbar_demux_006_src0_channel),        //          .channel
		.out_ready         (mux_pipeline_019_source0_ready),         //   source0.ready
		.out_valid         (mux_pipeline_019_source0_valid),         //          .valid
		.out_startofpacket (mux_pipeline_019_source0_startofpacket), //          .startofpacket
		.out_endofpacket   (mux_pipeline_019_source0_endofpacket),   //          .endofpacket
		.out_data          (mux_pipeline_019_source0_data),          //          .data
		.out_channel       (mux_pipeline_019_source0_channel),       //          .channel
		.in_empty          (1'b0),                                   // (terminated)
		.out_empty         (),                                       // (terminated)
		.out_error         (),                                       // (terminated)
		.in_error          (1'b0)                                    // (terminated)
	);

	q_sys_irq_mapper irq_mapper (
		.clk           (pcie_hard_ip_0_pcie_core_clk_clk),      //       clk.clk
		.reset         (~pcie_hard_ip_0_pcie_core_reset_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),              // receiver0.irq
		.sender_irq    (irq_synchronizer_receiver_irq)          //    sender.irq
	);

	altera_irq_clock_crosser #(
		.IRQ_WIDTH (16)
	) irq_synchronizer (
		.receiver_clk   (pcie_hard_ip_0_pcie_core_clk_clk),      //       receiver_clk.clk
		.sender_clk     (pcie_hard_ip_0_pcie_core_clk_clk),      //         sender_clk.clk
		.receiver_reset (~pcie_hard_ip_0_pcie_core_reset_reset), // receiver_clk_reset.reset
		.sender_reset   (~pcie_hard_ip_0_pcie_core_reset_reset), //   sender_clk_reset.reset
		.receiver_irq   (irq_synchronizer_receiver_irq),         //           receiver.irq
		.sender_irq     (pcie_hard_ip_0_rxm_irq_irq)             //             sender.irq
	);

endmodule
