// q_sys_pcie_hard_ip_0.v

// This file was auto-generated from altera_pcie_hard_ip_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 12.1sp1 243 at 2013.03.14.17:25:36

`timescale 1 ps / 1 ps
module q_sys_pcie_hard_ip_0 #(
		parameter       p_pcie_hip_type                     = "2",
		parameter[7:0]  lane_mask                           = 8'b11111110,
		parameter       max_link_width                      = 1,
		parameter       millisecond_cycle_count             = "125000",
		parameter       enable_gen2_core                    = "false",
		parameter       gen2_lane_rate_mode                 = "false",
		parameter       no_soft_reset                       = "false",
		parameter       core_clk_divider                    = 2,
		parameter       enable_ch0_pclk_out                 = "true",
		parameter       core_clk_source                     = "pclk",
		parameter       CB_P2A_AVALON_ADDR_B0               = 0,
		parameter       bar0_size_mask                      = 27,
		parameter       bar0_io_space                       = "false",
		parameter       bar0_64bit_mem_space                = "true",
		parameter       bar0_prefetchable                   = "true",
		parameter       CB_P2A_AVALON_ADDR_B1               = 0,
		parameter       bar1_size_mask                      = 0,
		parameter       bar1_io_space                       = "false",
		parameter       bar1_64bit_mem_space                = "true",
		parameter       bar1_prefetchable                   = "false",
		parameter       CB_P2A_AVALON_ADDR_B2               = 0,
		parameter       bar2_size_mask                      = 27,
		parameter       bar2_io_space                       = "false",
		parameter       bar2_64bit_mem_space                = "false",
		parameter       bar2_prefetchable                   = "false",
		parameter       CB_P2A_AVALON_ADDR_B3               = 0,
		parameter       bar3_size_mask                      = 0,
		parameter       bar3_io_space                       = "false",
		parameter       bar3_64bit_mem_space                = "false",
		parameter       bar3_prefetchable                   = "false",
		parameter       CB_P2A_AVALON_ADDR_B4               = 0,
		parameter       bar4_size_mask                      = 0,
		parameter       bar4_io_space                       = "false",
		parameter       bar4_64bit_mem_space                = "false",
		parameter       bar4_prefetchable                   = "false",
		parameter       CB_P2A_AVALON_ADDR_B5               = 0,
		parameter       bar5_size_mask                      = 0,
		parameter       bar5_io_space                       = "false",
		parameter       bar5_64bit_mem_space                = "false",
		parameter       bar5_prefetchable                   = "false",
		parameter       vendor_id                           = 4466,
		parameter       device_id                           = 57345,
		parameter       revision_id                         = 9,
		parameter       class_code                          = 16711680,
		parameter       subsystem_vendor_id                 = 4466,
		parameter       subsystem_device_id                 = 4420,
		parameter       port_link_number                    = 1,
		parameter       msi_function_count                  = 0,
		parameter       enable_msi_64bit_addressing         = "true",
		parameter       enable_function_msix_support        = "false",
		parameter       eie_before_nfts_count               = 4,
		parameter       enable_completion_timeout_disable   = "false",
		parameter       completion_timeout                  = "NONE",
		parameter       enable_adapter_half_rate_mode       = "false",
		parameter       msix_pba_bir                        = 0,
		parameter       msix_pba_offset                     = 0,
		parameter       msix_table_bir                      = 0,
		parameter       msix_table_offset                   = 0,
		parameter       msix_table_size                     = 0,
		parameter       use_crc_forwarding                  = "false",
		parameter       surprise_down_error_support         = "false",
		parameter       dll_active_report_support           = "false",
		parameter       bar_io_window_size                  = "32BIT",
		parameter       bar_prefetchable                    = 32,
		parameter[6:0]  hot_plug_support                    = 7'b0000000,
		parameter       no_command_completed                = "true",
		parameter       slot_power_limit                    = 0,
		parameter       slot_power_scale                    = 0,
		parameter       slot_number                         = 0,
		parameter       enable_slot_register                = "false",
		parameter       advanced_errors                     = "false",
		parameter       enable_ecrc_check                   = "false",
		parameter       enable_ecrc_gen                     = "false",
		parameter       max_payload_size                    = 1,
		parameter       retry_buffer_last_active_address    = 255,
		parameter       credit_buffer_allocation_aux        = "ABSOLUTE",
		parameter       vc0_rx_flow_ctrl_posted_header      = 13,
		parameter       vc0_rx_flow_ctrl_posted_data        = 107,
		parameter       vc0_rx_flow_ctrl_nonposted_header   = 8,
		parameter       vc0_rx_flow_ctrl_nonposted_data     = 0,
		parameter       vc0_rx_flow_ctrl_compl_header       = 48,
		parameter       vc0_rx_flow_ctrl_compl_data         = 256,
		parameter       RX_BUF                              = 9,
		parameter       RH_NUM                              = 7,
		parameter       G_TAG_NUM0                          = 32,
		parameter       endpoint_l0_latency                 = 0,
		parameter       endpoint_l1_latency                 = 0,
		parameter       enable_l1_aspm                      = "false",
		parameter       l01_entry_latency                   = 31,
		parameter       diffclock_nfts_count                = 255,
		parameter       sameclock_nfts_count                = 255,
		parameter       l1_exit_latency_sameclock           = 7,
		parameter       l1_exit_latency_diffclock           = 7,
		parameter       l0_exit_latency_sameclock           = 7,
		parameter       l0_exit_latency_diffclock           = 7,
		parameter       gen2_diffclock_nfts_count           = 255,
		parameter       gen2_sameclock_nfts_count           = 255,
		parameter       CG_COMMON_CLOCK_MODE                = 1,
		parameter       CB_PCIE_MODE                        = 0,
		parameter       AST_LITE                            = 0,
		parameter       CB_PCIE_RX_LITE                     = 0,
		parameter       CG_RXM_IRQ_NUM                      = 16,
		parameter       CG_AVALON_S_ADDR_WIDTH              = 20,
		parameter       bypass_tl                           = "false",
		parameter       CG_IMPL_CRA_AV_SLAVE_PORT           = 1,
		parameter       CG_NO_CPL_REORDERING                = 0,
		parameter       CG_ENABLE_A2P_INTERRUPT             = 0,
		parameter       CG_IRQ_BIT_ENA                      = 65535,
		parameter       CB_A2P_ADDR_MAP_IS_FIXED            = 0,
		parameter       CB_A2P_ADDR_MAP_NUM_ENTRIES         = 2,
		parameter       CB_A2P_ADDR_MAP_PASS_THRU_BITS      = 19,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW   = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW  = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH = 32'b00000000000000000000000000000000,
		parameter[31:0] CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW  = 32'b00000000000000000000000000000000,
		parameter       RXM_DATA_WIDTH                      = 64,
		parameter       RXM_BEN_WIDTH                       = 8,
		parameter       TL_SELECTION                        = 1,
		parameter       pcie_mode                           = "SHARED_MODE",
		parameter       single_rx_detect                    = 1,
		parameter       enable_coreclk_out_half_rate        = "false",
		parameter       low_priority_vc                     = 0,
		parameter       link_width                          = 1,
		parameter       cyclone4                            = 1
	) (
		output wire        pcie_core_clk_clk,                  //      pcie_core_clk.clk
		output wire        pcie_core_reset_reset_n,            //    pcie_core_reset.reset_n
		input  wire        cal_blk_clk_clk,                    //        cal_blk_clk.clk
		input  wire [19:0] txs_address,                        //                txs.address
		input  wire        txs_chipselect,                     //                   .chipselect
		input  wire [7:0]  txs_byteenable,                     //                   .byteenable
		output wire [63:0] txs_readdata,                       //                   .readdata
		input  wire [63:0] txs_writedata,                      //                   .writedata
		input  wire        txs_read,                           //                   .read
		input  wire        txs_write,                          //                   .write
		input  wire [6:0]  txs_burstcount,                     //                   .burstcount
		output wire        txs_readdatavalid,                  //                   .readdatavalid
		output wire        txs_waitrequest,                    //                   .waitrequest
		input  wire        refclk_export,                      //             refclk.export
		input  wire [39:0] test_in_test_in,                    //            test_in.test_in
		input  wire        pcie_rstn_export,                   //          pcie_rstn.export
		output wire        clocks_sim_clk250_export,           //         clocks_sim.clk250_export
		output wire        clocks_sim_clk500_export,           //                   .clk500_export
		output wire        clocks_sim_clk125_export,           //                   .clk125_export
		input  wire        reconfig_busy_busy_altgxb_reconfig, //      reconfig_busy.busy_altgxb_reconfig
		input  wire        pipe_ext_pipe_mode,                 //           pipe_ext.pipe_mode
		input  wire        pipe_ext_phystatus_ext,             //                   .phystatus_ext
		output wire        pipe_ext_rate_ext,                  //                   .rate_ext
		output wire [1:0]  pipe_ext_powerdown_ext,             //                   .powerdown_ext
		output wire        pipe_ext_txdetectrx_ext,            //                   .txdetectrx_ext
		input  wire        pipe_ext_rxelecidle0_ext,           //                   .rxelecidle0_ext
		input  wire [7:0]  pipe_ext_rxdata0_ext,               //                   .rxdata0_ext
		input  wire [2:0]  pipe_ext_rxstatus0_ext,             //                   .rxstatus0_ext
		input  wire        pipe_ext_rxvalid0_ext,              //                   .rxvalid0_ext
		input  wire        pipe_ext_rxdatak0_ext,              //                   .rxdatak0_ext
		output wire [7:0]  pipe_ext_txdata0_ext,               //                   .txdata0_ext
		output wire        pipe_ext_txdatak0_ext,              //                   .txdatak0_ext
		output wire        pipe_ext_rxpolarity0_ext,           //                   .rxpolarity0_ext
		output wire        pipe_ext_txcompl0_ext,              //                   .txcompl0_ext
		output wire        pipe_ext_txelecidle0_ext,           //                   .txelecidle0_ext
		input  wire        powerdown_pll_powerdown,            //          powerdown.pll_powerdown
		input  wire        powerdown_gxb_powerdown,            //                   .gxb_powerdown
		output wire [63:0] test_out_test_out,                  //           test_out.test_out
		output wire [31:0] bar1_0_address,                     //             bar1_0.address
		output wire        bar1_0_read,                        //                   .read
		input  wire        bar1_0_waitrequest,                 //                   .waitrequest
		output wire        bar1_0_write,                       //                   .write
		input  wire        bar1_0_readdatavalid,               //                   .readdatavalid
		input  wire [63:0] bar1_0_readdata,                    //                   .readdata
		output wire [63:0] bar1_0_writedata,                   //                   .writedata
		output wire [6:0]  bar1_0_burstcount,                  //                   .burstcount
		output wire [7:0]  bar1_0_byteenable,                  //                   .byteenable
		output wire [31:0] bar2_address,                       //               bar2.address
		output wire        bar2_read,                          //                   .read
		input  wire        bar2_waitrequest,                   //                   .waitrequest
		output wire        bar2_write,                         //                   .write
		input  wire        bar2_readdatavalid,                 //                   .readdatavalid
		input  wire [63:0] bar2_readdata,                      //                   .readdata
		output wire [63:0] bar2_writedata,                     //                   .writedata
		output wire [6:0]  bar2_burstcount,                    //                   .burstcount
		output wire [7:0]  bar2_byteenable,                    //                   .byteenable
		input  wire        cra_chipselect,                     //                cra.chipselect
		input  wire [11:0] cra_address,                        //                   .address
		input  wire [3:0]  cra_byteenable,                     //                   .byteenable
		input  wire        cra_read,                           //                   .read
		output wire [31:0] cra_readdata,                       //                   .readdata
		input  wire        cra_write,                          //                   .write
		input  wire [31:0] cra_writedata,                      //                   .writedata
		output wire        cra_waitrequest,                    //                   .waitrequest
		output wire        cra_irq_irq,                        //            cra_irq.irq
		input  wire [15:0] rxm_irq_irq,                        //            rxm_irq.irq
		input  wire        rx_in_rx_datain_0,                  //              rx_in.rx_datain_0
		output wire        tx_out_tx_dataout_0,                //             tx_out.tx_dataout_0
		input  wire [3:0]  reconfig_togxb_data,                //     reconfig_togxb.data
		input  wire        reconfig_gxbclk_clk,                //    reconfig_gxbclk.clk
		output wire [4:0]  reconfig_fromgxb_0_data,            // reconfig_fromgxb_0.data
		input  wire        fixedclk_clk                        //           fixedclk.clk
	);

	wire        reset_controller_internal_rx_digitalreset_serdes_interconect; // reset_controller_internal:rx_digitalreset_serdes -> altgx_internal:rx_digitalreset
	wire        pipe_interface_internal_txdatak_pcs_interconect;              // pipe_interface_internal:txdatak_pcs -> altgx_internal:tx_ctrlenable
	wire  [7:0] pipe_interface_internal_txdata_pcs_interconect;               // pipe_interface_internal:txdata_pcs -> altgx_internal:tx_datain
	wire        pipe_interface_internal_pclk_central_hip_interconect;         // pipe_interface_internal:pclk_central_hip -> pcie_internal_hip:pclk_central
	wire        pipe_interface_internal_pclk_ch0_hip_interconect;             // pipe_interface_internal:pclk_ch0_hip -> pcie_internal_hip:pclk_ch0
	wire        pipe_interface_internal_pll_fixed_clk_hip_interconect;        // pipe_interface_internal:pll_fixed_clk_hip -> pcie_internal_hip:pll_fixed_clk
	wire        pcie_internal_hip_l2_exit_interconect;                        // pcie_internal_hip:l2_exit -> reset_controller_internal:l2_exit
	wire        pcie_internal_hip_hotrst_exit_interconect;                    // pcie_internal_hip:hotrst_exit -> reset_controller_internal:hotrst_exit
	wire        pcie_internal_hip_dlup_exit_interconect;                      // pcie_internal_hip:dlup_exit -> reset_controller_internal:dlup_exit
	wire  [4:0] pcie_internal_hip_dl_ltssm_int_interconect;                   // pcie_internal_hip:dl_ltssm_int -> reset_controller_internal:ltssm
	wire        reset_controller_internal_srst_interconect;                   // reset_controller_internal:srst -> pcie_internal_hip:srst
	wire        reset_controller_internal_crst_interconect;                   // reset_controller_internal:crst -> pcie_internal_hip:crst
	wire        pipe_interface_internal_rc_pll_locked_interconect;            // pipe_interface_internal:rc_pll_locked -> reset_controller_internal:pll_locked
	wire        altgx_internal_rx_freqlocked_interconect;                     // altgx_internal:rx_freqlocked -> reset_controller_internal:rx_freqlocked
	wire        reset_controller_internal_txdigitalreset_interconect;         // reset_controller_internal:txdigitalreset -> altgx_internal:tx_digitalreset
	wire        reset_controller_internal_rxanalogreset_interconect;          // reset_controller_internal:rxanalogreset -> altgx_internal:rx_analogreset
	wire        pipe_interface_internal_rc_areset_interconect;                // pipe_interface_internal:rc_areset -> pcie_internal_hip:rc_areset
	wire  [7:0] altgx_internal_rx_dataout_interconect;                        // altgx_internal:rx_dataout -> pipe_interface_internal:rxdata_pcs
	wire        altgx_internal_pipephydonestatus_interconect;                 // altgx_internal:pipephydonestatus -> pipe_interface_internal:phystatus_pcs
	wire        altgx_internal_pipeelecidle_interconect;                      // altgx_internal:pipeelecidle -> pipe_interface_internal:rxelecidle_pcs
	wire        altgx_internal_pipedatavalid_interconect;                     // altgx_internal:pipedatavalid -> pipe_interface_internal:rxvalid_pcs
	wire  [2:0] altgx_internal_pipestatus_interconect;                        // altgx_internal:pipestatus -> pipe_interface_internal:rxstatus_pcs
	wire        altgx_internal_rx_ctrldetect_interconect;                     // altgx_internal:rx_ctrldetect -> pipe_interface_internal:rxdatak_pcs
	wire        pipe_interface_internal_gxb_powerdown_pcs_interconect;        // pipe_interface_internal:gxb_powerdown_pcs -> altgx_internal:gxb_powerdown
	wire        altgx_internal_hip_tx_clkout_0_interconect;                   // altgx_internal:hip_tx_clkout_0 -> pipe_interface_internal:hip_tx_clkout_pcs
	wire        reset_controller_internal_clk250_out_interconect;             // reset_controller_internal:clk250_out -> pipe_interface_internal:clk250_out
	wire        reset_controller_internal_clk500_out_interconect;             // reset_controller_internal:clk500_out -> pipe_interface_internal:clk500_out
	wire        pcie_internal_hip_rate_ext_interconect;                       // pcie_internal_hip:rate_ext -> pipe_interface_internal:rate_hip
	wire        altgx_internal_pll_locked_interconect;                        // altgx_internal:pll_locked -> pipe_interface_internal:pll_locked_pcs
	wire  [1:0] pipe_interface_internal_powerdown_pcs_interconect;            // pipe_interface_internal:powerdown_pcs -> altgx_internal:powerdn
	wire        pipe_interface_internal_rxpolarity_pcs_interconect;           // pipe_interface_internal:rxpolarity_pcs -> altgx_internal:pipe8b10binvpolarity
	wire        pipe_interface_internal_txcompl_pcs_interconect;              // pipe_interface_internal:txcompl_pcs -> altgx_internal:tx_forcedispcompliance
	wire        pipe_interface_internal_txdetectrx_pcs_interconect;           // pipe_interface_internal:txdetectrx_pcs -> altgx_internal:tx_detectrxloop
	wire        pipe_interface_internal_txelecidle_pcs_interconect;           // pipe_interface_internal:txelecidle_pcs -> altgx_internal:tx_forceelecidle
	wire        pipe_interface_internal_rxdatak_hip_0_interconect;            // pipe_interface_internal:rxdatak_hip_0 -> pcie_internal_hip:rxdatak0_ext
	wire  [2:0] pcie_internal_hip_eidle_infer_sel_0_interconect;              // pcie_internal_hip:eidle_infer_sel_0 -> altgx_internal:rx_elecidleinfersel_0
	wire  [7:0] pipe_interface_internal_rxdata_hip_0_interconect;             // pipe_interface_internal:rxdata_hip_0 -> pcie_internal_hip:rxdata0_ext
	wire        pipe_interface_internal_rxvalid_hip_0_interconect;            // pipe_interface_internal:rxvalid_hip_0 -> pcie_internal_hip:rxvalid0_ext
	wire        pipe_interface_internal_rxelecidle_hip_0_interconect;         // pipe_interface_internal:rxelecidle_hip_0 -> pcie_internal_hip:rxelecidle0_ext
	wire        pipe_interface_internal_phystatus_hip_0_interconect;          // pipe_interface_internal:phystatus_hip_0 -> pcie_internal_hip:phystatus0_ext
	wire  [2:0] pipe_interface_internal_rxstatus_hip_0_interconect;           // pipe_interface_internal:rxstatus_hip_0 -> pcie_internal_hip:rxstatus0_ext
	wire  [7:0] pcie_internal_hip_txdata0_ext_interconect;                    // pcie_internal_hip:txdata0_ext -> pipe_interface_internal:txdata0_hip
	wire        pcie_internal_hip_txdatak0_ext_interconect;                   // pcie_internal_hip:txdatak0_ext -> pipe_interface_internal:txdatak0_hip
	wire  [1:0] pcie_internal_hip_powerdown0_ext_interconect;                 // pcie_internal_hip:powerdown0_ext -> pipe_interface_internal:powerdown0_hip
	wire        pcie_internal_hip_rxpolarity0_ext_interconect;                // pcie_internal_hip:rxpolarity0_ext -> pipe_interface_internal:rxpolarity0_hip
	wire        pcie_internal_hip_txcompl0_ext_interconect;                   // pcie_internal_hip:txcompl0_ext -> pipe_interface_internal:txcompl0_hip
	wire        pcie_internal_hip_txdetectrx0_ext_interconect;                // pcie_internal_hip:txdetectrx0_ext -> pipe_interface_internal:txdetectrx0_hip
	wire        pcie_internal_hip_txelecidle0_ext_interconect;                // pcie_internal_hip:txelecidle0_ext -> pipe_interface_internal:txelecidle0_hip
	wire        rst_controller_reset_out_reset;                               // rst_controller:reset_out -> pcie_internal_hip:Rstn_i
	wire  [2:0] pcie_internal_hip_eidle_infer_sel;                            // port fragment
	wire  [4:0] pcie_internal_hip_dl_ltssm;                                   // port fragment
	wire  [0:0] altgx_internal_tx_dataout;                                    // port fragment
	wire  [0:0] altgx_internal_hip_tx_clkout;                                 // port fragment
	wire  [0:0] pipe_interface_internal_rxvalid_hip;                          // port fragment
	wire  [0:0] pipe_interface_internal_rxelecidle_hip;                       // port fragment
	wire  [7:0] pipe_interface_internal_rxdata_hip;                           // port fragment
	wire  [2:0] pipe_interface_internal_rxstatus_hip;                         // port fragment
	wire  [0:0] pipe_interface_internal_rxdatak_hip;                          // port fragment
	wire  [0:0] pipe_interface_internal_phystatus_hip;                        // port fragment

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (p_pcie_hip_type != "2")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					p_pcie_hip_type_check ( .error(1'b1) );
		end
		if (lane_mask != 8'b11111110)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					lane_mask_check ( .error(1'b1) );
		end
		if (max_link_width != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					max_link_width_check ( .error(1'b1) );
		end
		if (millisecond_cycle_count != "125000")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					millisecond_cycle_count_check ( .error(1'b1) );
		end
		if (enable_gen2_core != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_gen2_core_check ( .error(1'b1) );
		end
		if (gen2_lane_rate_mode != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					gen2_lane_rate_mode_check ( .error(1'b1) );
		end
		if (no_soft_reset != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					no_soft_reset_check ( .error(1'b1) );
		end
		if (core_clk_divider != 2)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					core_clk_divider_check ( .error(1'b1) );
		end
		if (enable_ch0_pclk_out != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_ch0_pclk_out_check ( .error(1'b1) );
		end
		if (core_clk_source != "pclk")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					core_clk_source_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B0 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b0_check ( .error(1'b1) );
		end
		if (bar0_size_mask != 27)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar0_size_mask_check ( .error(1'b1) );
		end
		if (bar0_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar0_io_space_check ( .error(1'b1) );
		end
		if (bar0_64bit_mem_space != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar0_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar0_prefetchable != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar0_prefetchable_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B1 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b1_check ( .error(1'b1) );
		end
		if (bar1_size_mask != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar1_size_mask_check ( .error(1'b1) );
		end
		if (bar1_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar1_io_space_check ( .error(1'b1) );
		end
		if (bar1_64bit_mem_space != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar1_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar1_prefetchable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar1_prefetchable_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B2 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b2_check ( .error(1'b1) );
		end
		if (bar2_size_mask != 27)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar2_size_mask_check ( .error(1'b1) );
		end
		if (bar2_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar2_io_space_check ( .error(1'b1) );
		end
		if (bar2_64bit_mem_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar2_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar2_prefetchable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar2_prefetchable_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B3 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b3_check ( .error(1'b1) );
		end
		if (bar3_size_mask != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar3_size_mask_check ( .error(1'b1) );
		end
		if (bar3_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar3_io_space_check ( .error(1'b1) );
		end
		if (bar3_64bit_mem_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar3_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar3_prefetchable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar3_prefetchable_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B4 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b4_check ( .error(1'b1) );
		end
		if (bar4_size_mask != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar4_size_mask_check ( .error(1'b1) );
		end
		if (bar4_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar4_io_space_check ( .error(1'b1) );
		end
		if (bar4_64bit_mem_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar4_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar4_prefetchable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar4_prefetchable_check ( .error(1'b1) );
		end
		if (CB_P2A_AVALON_ADDR_B5 != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_p2a_avalon_addr_b5_check ( .error(1'b1) );
		end
		if (bar5_size_mask != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar5_size_mask_check ( .error(1'b1) );
		end
		if (bar5_io_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar5_io_space_check ( .error(1'b1) );
		end
		if (bar5_64bit_mem_space != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar5_64bit_mem_space_check ( .error(1'b1) );
		end
		if (bar5_prefetchable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar5_prefetchable_check ( .error(1'b1) );
		end
		if (vendor_id != 4466)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vendor_id_check ( .error(1'b1) );
		end
		if (device_id != 57345)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					device_id_check ( .error(1'b1) );
		end
		if (revision_id != 9)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					revision_id_check ( .error(1'b1) );
		end
		if (class_code != 16711680)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					class_code_check ( .error(1'b1) );
		end
		if (subsystem_vendor_id != 4466)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					subsystem_vendor_id_check ( .error(1'b1) );
		end
		if (subsystem_device_id != 4420)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					subsystem_device_id_check ( .error(1'b1) );
		end
		if (port_link_number != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					port_link_number_check ( .error(1'b1) );
		end
		if (msi_function_count != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msi_function_count_check ( .error(1'b1) );
		end
		if (enable_msi_64bit_addressing != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_msi_64bit_addressing_check ( .error(1'b1) );
		end
		if (enable_function_msix_support != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_function_msix_support_check ( .error(1'b1) );
		end
		if (eie_before_nfts_count != 4)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					eie_before_nfts_count_check ( .error(1'b1) );
		end
		if (enable_completion_timeout_disable != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_completion_timeout_disable_check ( .error(1'b1) );
		end
		if (completion_timeout != "NONE")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					completion_timeout_check ( .error(1'b1) );
		end
		if (enable_adapter_half_rate_mode != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_adapter_half_rate_mode_check ( .error(1'b1) );
		end
		if (msix_pba_bir != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msix_pba_bir_check ( .error(1'b1) );
		end
		if (msix_pba_offset != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msix_pba_offset_check ( .error(1'b1) );
		end
		if (msix_table_bir != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msix_table_bir_check ( .error(1'b1) );
		end
		if (msix_table_offset != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msix_table_offset_check ( .error(1'b1) );
		end
		if (msix_table_size != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					msix_table_size_check ( .error(1'b1) );
		end
		if (use_crc_forwarding != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					use_crc_forwarding_check ( .error(1'b1) );
		end
		if (surprise_down_error_support != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					surprise_down_error_support_check ( .error(1'b1) );
		end
		if (dll_active_report_support != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					dll_active_report_support_check ( .error(1'b1) );
		end
		if (bar_io_window_size != "32BIT")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar_io_window_size_check ( .error(1'b1) );
		end
		if (bar_prefetchable != 32)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bar_prefetchable_check ( .error(1'b1) );
		end
		if (hot_plug_support != 7'b0000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					hot_plug_support_check ( .error(1'b1) );
		end
		if (no_command_completed != "true")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					no_command_completed_check ( .error(1'b1) );
		end
		if (slot_power_limit != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					slot_power_limit_check ( .error(1'b1) );
		end
		if (slot_power_scale != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					slot_power_scale_check ( .error(1'b1) );
		end
		if (slot_number != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					slot_number_check ( .error(1'b1) );
		end
		if (enable_slot_register != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_slot_register_check ( .error(1'b1) );
		end
		if (advanced_errors != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					advanced_errors_check ( .error(1'b1) );
		end
		if (enable_ecrc_check != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_ecrc_check_check ( .error(1'b1) );
		end
		if (enable_ecrc_gen != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_ecrc_gen_check ( .error(1'b1) );
		end
		if (max_payload_size != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					max_payload_size_check ( .error(1'b1) );
		end
		if (retry_buffer_last_active_address != 255)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					retry_buffer_last_active_address_check ( .error(1'b1) );
		end
		if (credit_buffer_allocation_aux != "ABSOLUTE")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					credit_buffer_allocation_aux_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_posted_header != 13)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_posted_header_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_posted_data != 107)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_posted_data_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_nonposted_header != 8)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_nonposted_header_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_nonposted_data != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_nonposted_data_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_compl_header != 48)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_compl_header_check ( .error(1'b1) );
		end
		if (vc0_rx_flow_ctrl_compl_data != 256)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					vc0_rx_flow_ctrl_compl_data_check ( .error(1'b1) );
		end
		if (RX_BUF != 9)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					rx_buf_check ( .error(1'b1) );
		end
		if (RH_NUM != 7)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					rh_num_check ( .error(1'b1) );
		end
		if (G_TAG_NUM0 != 32)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					g_tag_num0_check ( .error(1'b1) );
		end
		if (endpoint_l0_latency != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					endpoint_l0_latency_check ( .error(1'b1) );
		end
		if (endpoint_l1_latency != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					endpoint_l1_latency_check ( .error(1'b1) );
		end
		if (enable_l1_aspm != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_l1_aspm_check ( .error(1'b1) );
		end
		if (l01_entry_latency != 31)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					l01_entry_latency_check ( .error(1'b1) );
		end
		if (diffclock_nfts_count != 255)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					diffclock_nfts_count_check ( .error(1'b1) );
		end
		if (sameclock_nfts_count != 255)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					sameclock_nfts_count_check ( .error(1'b1) );
		end
		if (l1_exit_latency_sameclock != 7)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					l1_exit_latency_sameclock_check ( .error(1'b1) );
		end
		if (l1_exit_latency_diffclock != 7)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					l1_exit_latency_diffclock_check ( .error(1'b1) );
		end
		if (l0_exit_latency_sameclock != 7)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					l0_exit_latency_sameclock_check ( .error(1'b1) );
		end
		if (l0_exit_latency_diffclock != 7)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					l0_exit_latency_diffclock_check ( .error(1'b1) );
		end
		if (gen2_diffclock_nfts_count != 255)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					gen2_diffclock_nfts_count_check ( .error(1'b1) );
		end
		if (gen2_sameclock_nfts_count != 255)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					gen2_sameclock_nfts_count_check ( .error(1'b1) );
		end
		if (CG_COMMON_CLOCK_MODE != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_common_clock_mode_check ( .error(1'b1) );
		end
		if (CB_PCIE_MODE != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_pcie_mode_check ( .error(1'b1) );
		end
		if (AST_LITE != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					ast_lite_check ( .error(1'b1) );
		end
		if (CB_PCIE_RX_LITE != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_pcie_rx_lite_check ( .error(1'b1) );
		end
		if (CG_RXM_IRQ_NUM != 16)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_rxm_irq_num_check ( .error(1'b1) );
		end
		if (CG_AVALON_S_ADDR_WIDTH != 20)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_avalon_s_addr_width_check ( .error(1'b1) );
		end
		if (bypass_tl != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					bypass_tl_check ( .error(1'b1) );
		end
		if (CG_IMPL_CRA_AV_SLAVE_PORT != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_impl_cra_av_slave_port_check ( .error(1'b1) );
		end
		if (CG_NO_CPL_REORDERING != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_no_cpl_reordering_check ( .error(1'b1) );
		end
		if (CG_ENABLE_A2P_INTERRUPT != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_enable_a2p_interrupt_check ( .error(1'b1) );
		end
		if (CG_IRQ_BIT_ENA != 65535)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cg_irq_bit_ena_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_IS_FIXED != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_is_fixed_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_NUM_ENTRIES != 2)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_num_entries_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_PASS_THRU_BITS != 19)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_pass_thru_bits_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_0_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_0_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_1_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_1_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_2_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_2_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_3_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_3_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_4_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_4_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_5_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_5_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_6_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_6_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_7_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_7_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_8_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_8_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_9_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_9_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_10_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_10_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_11_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_11_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_12_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_12_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_13_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_13_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_14_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_14_low_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_15_high_check ( .error(1'b1) );
		end
		if (CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW != 32'b00000000000000000000000000000000)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cb_a2p_addr_map_fixed_table_15_low_check ( .error(1'b1) );
		end
		if (RXM_DATA_WIDTH != 64)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					rxm_data_width_check ( .error(1'b1) );
		end
		if (RXM_BEN_WIDTH != 8)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					rxm_ben_width_check ( .error(1'b1) );
		end
		if (TL_SELECTION != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					tl_selection_check ( .error(1'b1) );
		end
		if (pcie_mode != "SHARED_MODE")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					pcie_mode_check ( .error(1'b1) );
		end
		if (single_rx_detect != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					single_rx_detect_check ( .error(1'b1) );
		end
		if (enable_coreclk_out_half_rate != "false")
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_coreclk_out_half_rate_check ( .error(1'b1) );
		end
		if (low_priority_vc != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					low_priority_vc_check ( .error(1'b1) );
		end
		if (link_width != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					link_width_check ( .error(1'b1) );
		end
		if (cyclone4 != 1)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					cyclone4_check ( .error(1'b1) );
		end
	endgenerate

	altpcie_hip_pipen1b_qsys #(
		.INTENDED_DEVICE_FAMILY              ("Cyclone IV GX"),
		.pcie_qsys                           (1),
		.p_pcie_hip_type                     ("2"),
		.lane_mask                           (8'b11111110),
		.max_link_width                      (1),
		.millisecond_cycle_count             ("125000"),
		.enable_gen2_core                    ("false"),
		.gen2_lane_rate_mode                 ("false"),
		.no_soft_reset                       ("false"),
		.core_clk_divider                    (2),
		.enable_ch0_pclk_out                 ("true"),
		.core_clk_source                     ("pclk"),
		.CB_P2A_AVALON_ADDR_B0               (0),
		.bar0_size_mask                      (27),
		.bar0_io_space                       ("false"),
		.bar0_64bit_mem_space                ("true"),
		.bar0_prefetchable                   ("true"),
		.CB_P2A_AVALON_ADDR_B1               (0),
		.bar1_size_mask                      (0),
		.bar1_io_space                       ("false"),
		.bar1_64bit_mem_space                ("true"),
		.bar1_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B2               (0),
		.bar2_size_mask                      (27),
		.bar2_io_space                       ("false"),
		.bar2_64bit_mem_space                ("false"),
		.bar2_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B3               (0),
		.bar3_size_mask                      (0),
		.bar3_io_space                       ("false"),
		.bar3_64bit_mem_space                ("false"),
		.bar3_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B4               (0),
		.bar4_size_mask                      (0),
		.bar4_io_space                       ("false"),
		.bar4_64bit_mem_space                ("false"),
		.bar4_prefetchable                   ("false"),
		.CB_P2A_AVALON_ADDR_B5               (0),
		.bar5_size_mask                      (0),
		.bar5_io_space                       ("false"),
		.bar5_64bit_mem_space                ("false"),
		.bar5_prefetchable                   ("false"),
		.vendor_id                           (4466),
		.device_id                           (57345),
		.revision_id                         (9),
		.class_code                          (16711680),
		.subsystem_vendor_id                 (4466),
		.subsystem_device_id                 (4420),
		.port_link_number                    (1),
		.msi_function_count                  (0),
		.enable_msi_64bit_addressing         ("true"),
		.enable_function_msix_support        ("false"),
		.eie_before_nfts_count               (4),
		.enable_completion_timeout_disable   ("false"),
		.completion_timeout                  ("NONE"),
		.enable_adapter_half_rate_mode       ("false"),
		.msix_pba_bir                        (0),
		.msix_pba_offset                     (0),
		.msix_table_bir                      (0),
		.msix_table_offset                   (0),
		.msix_table_size                     (0),
		.use_crc_forwarding                  ("false"),
		.surprise_down_error_support         ("false"),
		.dll_active_report_support           ("false"),
		.bar_io_window_size                  ("32BIT"),
		.bar_prefetchable                    (32),
		.hot_plug_support                    (7'b0000000),
		.no_command_completed                ("true"),
		.slot_power_limit                    (0),
		.slot_power_scale                    (0),
		.slot_number                         (0),
		.enable_slot_register                ("false"),
		.advanced_errors                     ("false"),
		.enable_ecrc_check                   ("false"),
		.enable_ecrc_gen                     ("false"),
		.max_payload_size                    (1),
		.retry_buffer_last_active_address    (255),
		.credit_buffer_allocation_aux        ("BALANCED"),
		.vc0_rx_flow_ctrl_posted_header      (13),
		.vc0_rx_flow_ctrl_posted_data        (107),
		.vc0_rx_flow_ctrl_nonposted_header   (8),
		.vc0_rx_flow_ctrl_nonposted_data     (0),
		.vc0_rx_flow_ctrl_compl_header       (48),
		.vc0_rx_flow_ctrl_compl_data         (256),
		.RX_BUF                              (9),
		.RH_NUM                              (7),
		.G_TAG_NUM0                          (32),
		.endpoint_l0_latency                 (0),
		.endpoint_l1_latency                 (0),
		.enable_l1_aspm                      ("false"),
		.l01_entry_latency                   (31),
		.diffclock_nfts_count                (255),
		.sameclock_nfts_count                (255),
		.l1_exit_latency_sameclock           (7),
		.l1_exit_latency_diffclock           (7),
		.l0_exit_latency_sameclock           (7),
		.l0_exit_latency_diffclock           (7),
		.gen2_diffclock_nfts_count           (255),
		.gen2_sameclock_nfts_count           (255),
		.CG_COMMON_CLOCK_MODE                (1),
		.CB_PCIE_MODE                        (0),
		.AST_LITE                            (0),
		.CB_PCIE_RX_LITE                     (0),
		.CG_RXM_IRQ_NUM                      (16),
		.CG_AVALON_S_ADDR_WIDTH              (20),
		.bypass_tl                           ("false"),
		.CG_IMPL_CRA_AV_SLAVE_PORT           (1),
		.CG_NO_CPL_REORDERING                (0),
		.CG_ENABLE_A2P_INTERRUPT             (0),
		.CG_IRQ_BIT_ENA                      (65535),
		.CB_A2P_ADDR_MAP_IS_FIXED            (0),
		.CB_A2P_ADDR_MAP_NUM_ENTRIES         (2),
		.CB_A2P_ADDR_MAP_PASS_THRU_BITS      (19),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW   (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW  (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH (32'b00000000000000000000000000000000),
		.CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW  (32'b00000000000000000000000000000000),
		.RXM_DATA_WIDTH                      (64),
		.RXM_BEN_WIDTH                       (8),
		.TL_SELECTION                        (1),
		.pcie_mode                           ("SHARED_MODE"),
		.single_rx_detect                    (1),
		.enable_coreclk_out_half_rate        ("false"),
		.low_priority_vc                     (0)
	) pcie_internal_hip (
		.npor                            (pcie_rstn_export),                                                     //               npor.interconect
		.dl_ltssm                        (pcie_internal_hip_dl_ltssm),                                           //       dl_ltssm_int.interconect
		.dlup_exit                       (pcie_internal_hip_dlup_exit_interconect),                              //          dlup_exit.interconect
		.hotrst_exit                     (pcie_internal_hip_hotrst_exit_interconect),                            //        hotrst_exit.interconect
		.l2_exit                         (pcie_internal_hip_l2_exit_interconect),                                //            l2_exit.interconect
		.powerdown0_ext                  (pcie_internal_hip_powerdown0_ext_interconect),                         //     powerdown0_ext.interconect
		.rate_ext                        (pcie_internal_hip_rate_ext_interconect),                               //           rate_ext.interconect
		.rc_rx_analogreset               (),                                                                     //  rc_rx_analogreset.interconect
		.rc_rx_digitalreset              (),                                                                     // rc_rx_digitalreset.interconect
		.rxpolarity0_ext                 (pcie_internal_hip_rxpolarity0_ext_interconect),                        //    rxpolarity0_ext.interconect
		.txcompl0_ext                    (pcie_internal_hip_txcompl0_ext_interconect),                           //       txcompl0_ext.interconect
		.txdata0_ext                     (pcie_internal_hip_txdata0_ext_interconect),                            //        txdata0_ext.interconect
		.txdatak0_ext                    (pcie_internal_hip_txdatak0_ext_interconect),                           //       txdatak0_ext.interconect
		.txdetectrx0_ext                 (pcie_internal_hip_txdetectrx0_ext_interconect),                        //    txdetectrx0_ext.interconect
		.txelecidle0_ext                 (pcie_internal_hip_txelecidle0_ext_interconect),                        //    txelecidle0_ext.interconect
		.crst                            (reset_controller_internal_crst_interconect),                           //               crst.interconect
		.pclk_central                    (pipe_interface_internal_pclk_central_hip_interconect),                 //       pclk_central.interconect
		.pclk_ch0                        (pipe_interface_internal_pclk_ch0_hip_interconect),                     //           pclk_ch0.interconect
		.pld_clk                         (pcie_core_clk_clk),                                                    //            pld_clk.clk
		.pll_fixed_clk                   (pipe_interface_internal_pll_fixed_clk_hip_interconect),                //      pll_fixed_clk.interconect
		.rc_areset                       (pipe_interface_internal_rc_areset_interconect),                        //          rc_areset.interconect
		.srst                            (reset_controller_internal_srst_interconect),                           //               srst.interconect
		.test_in                         (test_in_test_in),                                                      //            test_in.interconect
		.AvlClk_i                        (pcie_core_clk_clk),                                                    //         avalon_clk.clk
		.Rstn_i                          (~rst_controller_reset_out_reset),                                      //       avalon_reset.reset_n
		.TxsAddress_i                    (txs_address),                                                          //                Txs.address
		.TxsChipSelect_i                 (txs_chipselect),                                                       //                   .chipselect
		.TxsByteEnable_i                 (txs_byteenable),                                                       //                   .byteenable
		.TxsReadData_o                   (txs_readdata),                                                         //                   .readdata
		.TxsWriteData_i                  (txs_writedata),                                                        //                   .writedata
		.TxsRead_i                       (txs_read),                                                             //                   .read
		.TxsWrite_i                      (txs_write),                                                            //                   .write
		.TxsBurstCount_i                 (txs_burstcount),                                                       //                   .burstcount
		.TxsReadDataValid_o              (txs_readdatavalid),                                                    //                   .readdatavalid
		.TxsWaitRequest_o                (txs_waitrequest),                                                      //                   .waitrequest
		.CraChipSelect_i                 (cra_chipselect),                                                       //                Cra.chipselect
		.CraAddress_i                    (cra_address),                                                          //                   .address
		.CraByteEnable_i                 (cra_byteenable),                                                       //                   .byteenable
		.CraRead                         (cra_read),                                                             //                   .read
		.CraReadData_o                   (cra_readdata),                                                         //                   .readdata
		.CraWrite                        (cra_write),                                                            //                   .write
		.CraWriteData_i                  (cra_writedata),                                                        //                   .writedata
		.CraWaitRequest_o                (cra_waitrequest),                                                      //                   .waitrequest
		.CraIrq_o                        (cra_irq_irq),                                                          //             CraIrq.irq
		.core_clk_out                    (pcie_core_clk_clk),                                                    //      pcie_core_clk.clk
		.eidle_infer_sel                 (pcie_internal_hip_eidle_infer_sel),                                    //  eidle_infer_sel_0.interconect
		.tx_deemph_0                     (),                                                                     //        tx_deemph_0.interconect
		.tx_margin_0                     (),                                                                     //        tx_margin_0.interconect
		.phystatus0_ext                  (pipe_interface_internal_phystatus_hip_0_interconect),                  //     phystatus0_ext.interconect
		.rxdata0_ext                     (pipe_interface_internal_rxdata_hip_0_interconect),                     //        rxdata0_ext.interconect
		.rxdatak0_ext                    (pipe_interface_internal_rxdatak_hip_0_interconect),                    //       rxdatak0_ext.interconect
		.rxelecidle0_ext                 (pipe_interface_internal_rxelecidle_hip_0_interconect),                 //    rxelecidle0_ext.interconect
		.rxstatus0_ext                   (pipe_interface_internal_rxstatus_hip_0_interconect),                   //      rxstatus0_ext.interconect
		.rxvalid0_ext                    (pipe_interface_internal_rxvalid_hip_0_interconect),                    //       rxvalid0_ext.interconect
		.test_out                        (test_out_test_out),                                                    //    test_out_export.test_out
		.RxmAddress_0_o                  (bar1_0_address),                                                       //           Rxm_BAR0.address
		.RxmRead_0_o                     (bar1_0_read),                                                          //                   .read
		.RxmWaitRequest_0_i              (bar1_0_waitrequest),                                                   //                   .waitrequest
		.RxmWrite_0_o                    (bar1_0_write),                                                         //                   .write
		.RxmReadDataValid_0_i            (bar1_0_readdatavalid),                                                 //                   .readdatavalid
		.RxmReadData_0_i                 (bar1_0_readdata),                                                      //                   .readdata
		.RxmWriteData_0_o                (bar1_0_writedata),                                                     //                   .writedata
		.RxmBurstCount_0_o               (bar1_0_burstcount),                                                    //                   .burstcount
		.RxmByteEnable_0_o               (bar1_0_byteenable),                                                    //                   .byteenable
		.RxmAddress_2_o                  (bar2_address),                                                         //           Rxm_BAR2.address
		.RxmRead_2_o                     (bar2_read),                                                            //                   .read
		.RxmWaitRequest_2_i              (bar2_waitrequest),                                                     //                   .waitrequest
		.RxmWrite_2_o                    (bar2_write),                                                           //                   .write
		.RxmReadDataValid_2_i            (bar2_readdatavalid),                                                   //                   .readdatavalid
		.RxmReadData_2_i                 (bar2_readdata),                                                        //                   .readdata
		.RxmWriteData_2_o                (bar2_writedata),                                                       //                   .writedata
		.RxmBurstCount_2_o               (bar2_burstcount),                                                      //                   .burstcount
		.RxmByteEnable_2_o               (bar2_byteenable),                                                      //                   .byteenable
		.RxmIrq_i                        (rxm_irq_irq),                                                          //             RxmIrq.irq
		.app_int_ack                     (),                                                                     //        (terminated)
		.app_msi_ack                     (),                                                                     //        (terminated)
		.avs_pcie_reconfig_readdata      (),                                                                     //        (terminated)
		.avs_pcie_reconfig_readdatavalid (),                                                                     //        (terminated)
		.avs_pcie_reconfig_waitrequest   (),                                                                     //        (terminated)
		.derr_cor_ext_rcv0               (),                                                                     //        (terminated)
		.derr_cor_ext_rcv1               (),                                                                     //        (terminated)
		.derr_cor_ext_rpl                (),                                                                     //        (terminated)
		.derr_rpl                        (),                                                                     //        (terminated)
		.ev_128ns                        (),                                                                     //        (terminated)
		.ev_1us                          (),                                                                     //        (terminated)
		.hip_extraclkout                 (),                                                                     //        (terminated)
		.int_status                      (),                                                                     //        (terminated)
		.lmi_ack                         (),                                                                     //        (terminated)
		.lmi_dout                        (),                                                                     //        (terminated)
		.npd_alloc_1cred_vc0             (),                                                                     //        (terminated)
		.npd_alloc_1cred_vc1             (),                                                                     //        (terminated)
		.npd_cred_vio_vc0                (),                                                                     //        (terminated)
		.npd_cred_vio_vc1                (),                                                                     //        (terminated)
		.nph_alloc_1cred_vc0             (),                                                                     //        (terminated)
		.nph_alloc_1cred_vc1             (),                                                                     //        (terminated)
		.nph_cred_vio_vc0                (),                                                                     //        (terminated)
		.nph_cred_vio_vc1                (),                                                                     //        (terminated)
		.pme_to_sr                       (),                                                                     //        (terminated)
		.powerdown1_ext                  (),                                                                     //        (terminated)
		.powerdown2_ext                  (),                                                                     //        (terminated)
		.powerdown3_ext                  (),                                                                     //        (terminated)
		.powerdown4_ext                  (),                                                                     //        (terminated)
		.powerdown5_ext                  (),                                                                     //        (terminated)
		.powerdown6_ext                  (),                                                                     //        (terminated)
		.powerdown7_ext                  (),                                                                     //        (terminated)
		.r2c_err0                        (),                                                                     //        (terminated)
		.r2c_err1                        (),                                                                     //        (terminated)
		.rc_gxb_powerdown                (),                                                                     //        (terminated)
		.rc_tx_digitalreset              (),                                                                     //        (terminated)
		.reset_status                    (),                                                                     //        (terminated)
		.rx_fifo_empty0                  (),                                                                     //        (terminated)
		.rx_fifo_empty1                  (),                                                                     //        (terminated)
		.rx_fifo_full0                   (),                                                                     //        (terminated)
		.rx_fifo_full1                   (),                                                                     //        (terminated)
		.rx_st_bardec0                   (),                                                                     //        (terminated)
		.rx_st_bardec1                   (),                                                                     //        (terminated)
		.rx_st_be0                       (),                                                                     //        (terminated)
		.rx_st_be0_p1                    (),                                                                     //        (terminated)
		.rx_st_be1                       (),                                                                     //        (terminated)
		.rx_st_be1_p1                    (),                                                                     //        (terminated)
		.rx_st_data0                     (),                                                                     //        (terminated)
		.rx_st_data0_p1                  (),                                                                     //        (terminated)
		.rx_st_data1                     (),                                                                     //        (terminated)
		.rx_st_data1_p1                  (),                                                                     //        (terminated)
		.rx_st_eop0                      (),                                                                     //        (terminated)
		.rx_st_eop0_p1                   (),                                                                     //        (terminated)
		.rx_st_eop1                      (),                                                                     //        (terminated)
		.rx_st_eop1_p1                   (),                                                                     //        (terminated)
		.rx_st_err0                      (),                                                                     //        (terminated)
		.rx_st_err1                      (),                                                                     //        (terminated)
		.rx_st_sop0                      (),                                                                     //        (terminated)
		.rx_st_sop0_p1                   (),                                                                     //        (terminated)
		.rx_st_sop1                      (),                                                                     //        (terminated)
		.rx_st_sop1_p1                   (),                                                                     //        (terminated)
		.rx_st_valid0                    (),                                                                     //        (terminated)
		.rx_st_valid1                    (),                                                                     //        (terminated)
		.rxpolarity1_ext                 (),                                                                     //        (terminated)
		.rxpolarity2_ext                 (),                                                                     //        (terminated)
		.rxpolarity3_ext                 (),                                                                     //        (terminated)
		.rxpolarity4_ext                 (),                                                                     //        (terminated)
		.rxpolarity5_ext                 (),                                                                     //        (terminated)
		.rxpolarity6_ext                 (),                                                                     //        (terminated)
		.rxpolarity7_ext                 (),                                                                     //        (terminated)
		.serr_out                        (),                                                                     //        (terminated)
		.suc_spd_neg                     (),                                                                     //        (terminated)
		.swdn_wake                       (),                                                                     //        (terminated)
		.swup_hotrst                     (),                                                                     //        (terminated)
		.tl_cfg_add                      (),                                                                     //        (terminated)
		.tl_cfg_ctl                      (),                                                                     //        (terminated)
		.tl_cfg_ctl_wr                   (),                                                                     //        (terminated)
		.tl_cfg_sts                      (),                                                                     //        (terminated)
		.tl_cfg_sts_wr                   (),                                                                     //        (terminated)
		.tlbp_dl_ack_phypm               (),                                                                     //        (terminated)
		.tlbp_dl_ack_requpfc             (),                                                                     //        (terminated)
		.tlbp_dl_ack_sndupfc             (),                                                                     //        (terminated)
		.tlbp_dl_current_deemp           (),                                                                     //        (terminated)
		.tlbp_dl_currentspeed            (),                                                                     //        (terminated)
		.tlbp_dl_dll_req                 (),                                                                     //        (terminated)
		.tlbp_dl_err_dll                 (),                                                                     //        (terminated)
		.tlbp_dl_errphy                  (),                                                                     //        (terminated)
		.tlbp_dl_link_autobdw_status     (),                                                                     //        (terminated)
		.tlbp_dl_link_bdwmng_status      (),                                                                     //        (terminated)
		.tlbp_dl_rpbuf_emp               (),                                                                     //        (terminated)
		.tlbp_dl_rst_enter_comp_bit      (),                                                                     //        (terminated)
		.tlbp_dl_rst_tx_margin_field     (),                                                                     //        (terminated)
		.tlbp_dl_rx_typ_pm               (),                                                                     //        (terminated)
		.tlbp_dl_rx_valpm                (),                                                                     //        (terminated)
		.tlbp_dl_tx_ackpm                (),                                                                     //        (terminated)
		.tlbp_dl_up                      (),                                                                     //        (terminated)
		.tlbp_dl_vc_status               (),                                                                     //        (terminated)
		.tlbp_link_up                    (),                                                                     //        (terminated)
		.tx_cred0                        (),                                                                     //        (terminated)
		.tx_cred1                        (),                                                                     //        (terminated)
		.tx_fifo_empty0                  (),                                                                     //        (terminated)
		.tx_fifo_empty1                  (),                                                                     //        (terminated)
		.tx_fifo_full0                   (),                                                                     //        (terminated)
		.tx_fifo_full1                   (),                                                                     //        (terminated)
		.tx_fifo_rdptr0                  (),                                                                     //        (terminated)
		.tx_fifo_rdptr1                  (),                                                                     //        (terminated)
		.tx_fifo_wrptr0                  (),                                                                     //        (terminated)
		.tx_fifo_wrptr1                  (),                                                                     //        (terminated)
		.tx_st_ready0                    (),                                                                     //        (terminated)
		.tx_st_ready1                    (),                                                                     //        (terminated)
		.txcompl1_ext                    (),                                                                     //        (terminated)
		.txcompl2_ext                    (),                                                                     //        (terminated)
		.txcompl3_ext                    (),                                                                     //        (terminated)
		.txcompl4_ext                    (),                                                                     //        (terminated)
		.txcompl5_ext                    (),                                                                     //        (terminated)
		.txcompl6_ext                    (),                                                                     //        (terminated)
		.txcompl7_ext                    (),                                                                     //        (terminated)
		.txdata1_ext                     (),                                                                     //        (terminated)
		.txdata2_ext                     (),                                                                     //        (terminated)
		.txdata3_ext                     (),                                                                     //        (terminated)
		.txdata4_ext                     (),                                                                     //        (terminated)
		.txdata5_ext                     (),                                                                     //        (terminated)
		.txdata6_ext                     (),                                                                     //        (terminated)
		.txdata7_ext                     (),                                                                     //        (terminated)
		.txdatak1_ext                    (),                                                                     //        (terminated)
		.txdatak2_ext                    (),                                                                     //        (terminated)
		.txdatak3_ext                    (),                                                                     //        (terminated)
		.txdatak4_ext                    (),                                                                     //        (terminated)
		.txdatak5_ext                    (),                                                                     //        (terminated)
		.txdatak6_ext                    (),                                                                     //        (terminated)
		.txdatak7_ext                    (),                                                                     //        (terminated)
		.txdetectrx1_ext                 (),                                                                     //        (terminated)
		.txdetectrx2_ext                 (),                                                                     //        (terminated)
		.txdetectrx3_ext                 (),                                                                     //        (terminated)
		.txdetectrx4_ext                 (),                                                                     //        (terminated)
		.txdetectrx5_ext                 (),                                                                     //        (terminated)
		.txdetectrx6_ext                 (),                                                                     //        (terminated)
		.txdetectrx7_ext                 (),                                                                     //        (terminated)
		.txelecidle1_ext                 (),                                                                     //        (terminated)
		.txelecidle2_ext                 (),                                                                     //        (terminated)
		.txelecidle3_ext                 (),                                                                     //        (terminated)
		.txelecidle4_ext                 (),                                                                     //        (terminated)
		.txelecidle5_ext                 (),                                                                     //        (terminated)
		.txelecidle6_ext                 (),                                                                     //        (terminated)
		.txelecidle7_ext                 (),                                                                     //        (terminated)
		.use_pcie_reconfig               (),                                                                     //        (terminated)
		.wake_oen                        (),                                                                     //        (terminated)
		.aer_msi_num                     (5'b00000),                                                             //        (terminated)
		.app_int_sts                     (1'b0),                                                                 //        (terminated)
		.app_msi_num                     (5'b00000),                                                             //        (terminated)
		.app_msi_req                     (1'b0),                                                                 //        (terminated)
		.app_msi_tc                      (3'b000),                                                               //        (terminated)
		.avs_pcie_reconfig_address       (8'b00000000),                                                          //        (terminated)
		.avs_pcie_reconfig_chipselect    (1'b0),                                                                 //        (terminated)
		.avs_pcie_reconfig_clk           (1'b0),                                                                 //        (terminated)
		.avs_pcie_reconfig_read          (1'b0),                                                                 //        (terminated)
		.avs_pcie_reconfig_rstn          (1'b0),                                                                 //        (terminated)
		.avs_pcie_reconfig_write         (1'b0),                                                                 //        (terminated)
		.avs_pcie_reconfig_writedata     (16'b0000000000000000),                                                 //        (terminated)
		.core_clk_in                     (1'b0),                                                                 //        (terminated)
		.cpl_err                         (7'b0000000),                                                           //        (terminated)
		.cpl_pending                     (1'b0),                                                                 //        (terminated)
		.dbg_pipex1_rx                   (15'b000000000000000),                                                  //        (terminated)
		.hpg_ctrler                      (5'b00000),                                                             //        (terminated)
		.lmi_addr                        (12'b000000000000),                                                     //        (terminated)
		.lmi_din                         (32'b00000000000000000000000000000000),                                 //        (terminated)
		.lmi_rden                        (1'b0),                                                                 //        (terminated)
		.lmi_wren                        (1'b0),                                                                 //        (terminated)
		.mode                            (2'b00),                                                                //        (terminated)
		.pex_msi_num                     (5'b00000),                                                             //        (terminated)
		.pm_auxpwr                       (1'b0),                                                                 //        (terminated)
		.pm_data                         (10'b0000000000),                                                       //        (terminated)
		.pm_event                        (1'b0),                                                                 //        (terminated)
		.pme_to_cr                       (1'b0),                                                                 //        (terminated)
		.rc_inclk_eq_125mhz              (1'b0),                                                                 //        (terminated)
		.rc_pll_locked                   (1'b1),                                                                 //        (terminated)
		.rc_rx_pll_locked_one            (1'b1),                                                                 //        (terminated)
		.rx_st_mask0                     (1'b0),                                                                 //        (terminated)
		.rx_st_mask1                     (1'b0),                                                                 //        (terminated)
		.rx_st_ready0                    (1'b0),                                                                 //        (terminated)
		.rx_st_ready1                    (1'b0),                                                                 //        (terminated)
		.swdn_in                         (3'b000),                                                               //        (terminated)
		.swup_in                         (7'b0000000),                                                           //        (terminated)
		.tl_slotclk_cfg                  (1'b1),                                                                 //        (terminated)
		.tlbp_dl_aspm_cr0                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_comclk_reg              (1'b0),                                                                 //        (terminated)
		.tlbp_dl_ctrl_link2              (13'b0000000000000),                                                    //        (terminated)
		.tlbp_dl_data_upfc               (12'b000000000000),                                                     //        (terminated)
		.tlbp_dl_hdr_upfc                (8'b00000000),                                                          //        (terminated)
		.tlbp_dl_inh_dllp                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_maxpload_dcr            (3'b000),                                                               //        (terminated)
		.tlbp_dl_req_phycfg              (4'b0000),                                                              //        (terminated)
		.tlbp_dl_req_phypm               (4'b0000),                                                              //        (terminated)
		.tlbp_dl_req_upfc                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_req_wake                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_rx_ecrcchk              (1'b0),                                                                 //        (terminated)
		.tlbp_dl_snd_upfc                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_tx_reqpm                (1'b0),                                                                 //        (terminated)
		.tlbp_dl_tx_typpm                (3'b000),                                                               //        (terminated)
		.tlbp_dl_txcfg_extsy             (1'b0),                                                                 //        (terminated)
		.tlbp_dl_typ_upfc                (2'b00),                                                                //        (terminated)
		.tlbp_dl_vc_ctrl                 (8'b00000000),                                                          //        (terminated)
		.tlbp_dl_vcid_map                (24'b000000000000000000000000),                                         //        (terminated)
		.tlbp_dl_vcid_upfc               (3'b000),                                                               //        (terminated)
		.tx_st_data0                     (64'b0000000000000000000000000000000000000000000000000000000000000000), //        (terminated)
		.tx_st_data0_p1                  (64'b0000000000000000000000000000000000000000000000000000000000000000), //        (terminated)
		.tx_st_data1                     (64'b0000000000000000000000000000000000000000000000000000000000000000), //        (terminated)
		.tx_st_data1_p1                  (64'b0000000000000000000000000000000000000000000000000000000000000000), //        (terminated)
		.tx_st_eop0                      (1'b0),                                                                 //        (terminated)
		.tx_st_eop0_p1                   (1'b0),                                                                 //        (terminated)
		.tx_st_eop1                      (1'b0),                                                                 //        (terminated)
		.tx_st_eop1_p1                   (1'b0),                                                                 //        (terminated)
		.tx_st_err0                      (1'b0),                                                                 //        (terminated)
		.tx_st_err1                      (1'b0),                                                                 //        (terminated)
		.tx_st_sop0                      (1'b0),                                                                 //        (terminated)
		.tx_st_sop0_p1                   (1'b0),                                                                 //        (terminated)
		.tx_st_sop1                      (1'b0),                                                                 //        (terminated)
		.tx_st_sop1_p1                   (1'b0),                                                                 //        (terminated)
		.tx_st_valid0                    (1'b0),                                                                 //        (terminated)
		.tx_st_valid1                    (1'b0),                                                                 //        (terminated)
		.phystatus1_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata1_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak1_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle1_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus1_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid1_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus2_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata2_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak2_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle2_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus2_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid2_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus3_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata3_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak3_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle3_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus3_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid3_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus4_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata4_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak4_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle4_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus4_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid4_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus5_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata5_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak5_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle5_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus5_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid5_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus6_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata6_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak6_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle6_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus6_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid6_ext                    (1'b0),                                                                 //        (terminated)
		.phystatus7_ext                  (1'b0),                                                                 //        (terminated)
		.rxdata7_ext                     (8'b00000000),                                                          //        (terminated)
		.rxdatak7_ext                    (1'b0),                                                                 //        (terminated)
		.rxelecidle7_ext                 (1'b0),                                                                 //        (terminated)
		.rxstatus7_ext                   (3'b000),                                                               //        (terminated)
		.rxvalid7_ext                    (1'b0)                                                                  //        (terminated)
	);

	q_sys_pcie_hard_ip_0_altgx_internal altgx_internal (
		.cal_blk_clk            (cal_blk_clk_clk),                                              //            cal_blk_clk.clk
		.gxb_powerdown          (pipe_interface_internal_gxb_powerdown_pcs_interconect),        //          gxb_powerdown.interconect
		.pipe8b10binvpolarity   (pipe_interface_internal_rxpolarity_pcs_interconect),           //   pipe8b10binvpolarity.interconect
		.pll_inclk              (refclk_export),                                                //              pll_inclk.interconect
		.powerdn                (pipe_interface_internal_powerdown_pcs_interconect),            //                powerdn.interconect
		.rx_analogreset         (reset_controller_internal_rxanalogreset_interconect),          //         rx_analogreset.interconect
		.fixedclk               (fixedclk_clk),                                                 //        fixedclk_export.clk
		.reconfig_togxb         (reconfig_togxb_data),                                          //           togxb_export.data
		.reconfig_fromgxb       (reconfig_fromgxb_0_data),                                      //       fromgxb_export_0.data
		.reconfig_clk           (reconfig_gxbclk_clk),                                          //    reconfig_clk_export.clk
		.rx_dataout             (altgx_internal_rx_dataout_interconect),                        //             rx_dataout.interconect
		.rx_digitalreset        (reset_controller_internal_rx_digitalreset_serdes_interconect), //        rx_digitalreset.interconect
		.rx_elecidleinfersel    ({pcie_internal_hip_eidle_infer_sel_0_interconect[2:0]}),       //  rx_elecidleinfersel_0.interconect
		.tx_ctrlenable          (pipe_interface_internal_txdatak_pcs_interconect),              //          tx_ctrlenable.interconect
		.tx_datain              (pipe_interface_internal_txdata_pcs_interconect),               //              tx_datain.interconect
		.tx_detectrxloop        (pipe_interface_internal_txdetectrx_pcs_interconect),           //        tx_detectrxloop.interconect
		.tx_forcedispcompliance (pipe_interface_internal_txcompl_pcs_interconect),              // tx_forcedispcompliance.interconect
		.tx_forceelecidle       (pipe_interface_internal_txelecidle_pcs_interconect),           //       tx_forceelecidle.interconect
		.hip_tx_clkout          (altgx_internal_hip_tx_clkout),                                 //        hip_tx_clkout_0.interconect
		.pipedatavalid          (altgx_internal_pipedatavalid_interconect),                     //          pipedatavalid.interconect
		.pipephydonestatus      (altgx_internal_pipephydonestatus_interconect),                 //      pipephydonestatus.interconect
		.pipeelecidle           (altgx_internal_pipeelecidle_interconect),                      //           pipeelecidle.interconect
		.pipestatus             (altgx_internal_pipestatus_interconect),                        //             pipestatus.interconect
		.pll_locked             (altgx_internal_pll_locked_interconect),                        //             pll_locked.interconect
		.rx_ctrldetect          (altgx_internal_rx_ctrldetect_interconect),                     //          rx_ctrldetect.interconect
		.rx_freqlocked          (altgx_internal_rx_freqlocked_interconect),                     //          rx_freqlocked.interconect
		.tx_digitalreset        (reset_controller_internal_txdigitalreset_interconect),         //        tx_digitalreset.interconect
		.rx_datain              ({rx_in_rx_datain_0}),                                          //           rx_in_export.rx_datain_0
		.tx_dataout             (altgx_internal_tx_dataout),                                    //          tx_out_export.tx_dataout_0
		.rx_patterndetect       (),                                                             //            (terminated)
		.rx_syncstatus          ()                                                              //            (terminated)
	);

	altera_pcie_hard_ip_reset_controller #(
		.link_width (1),
		.cyclone4   (1)
	) reset_controller_internal (
		.clk250_export          (clocks_sim_clk250_export),                                     // reset_controller_export.clk250_export
		.clk500_export          (clocks_sim_clk500_export),                                     //                        .clk500_export
		.clk125_export          (clocks_sim_clk125_export),                                     //                        .clk125_export
		.busy_altgxb_reconfig   (reconfig_busy_busy_altgxb_reconfig),                           //    reconfig_busy_export.busy_altgxb_reconfig
		.pld_clk                (pcie_core_clk_clk),                                            //                 pld_clk.clk
		.reset_n_out            (pcie_core_reset_reset_n),                                      //             reset_n_out.reset_n
		.pcie_rstn              (pcie_rstn_export),                                             //               pcie_rstn.interconect
		.refclk                 (refclk_export),                                                //                  refclk.interconect
		.l2_exit                (pcie_internal_hip_l2_exit_interconect),                        //                 l2_exit.interconect
		.hotrst_exit            (pcie_internal_hip_hotrst_exit_interconect),                    //             hotrst_exit.interconect
		.dlup_exit              (pcie_internal_hip_dlup_exit_interconect),                      //               dlup_exit.interconect
		.ltssm                  (pcie_internal_hip_dl_ltssm_int_interconect),                   //                   ltssm.interconect
		.pll_locked             (pipe_interface_internal_rc_pll_locked_interconect),            //              pll_locked.interconect
		.rx_freqlocked          (altgx_internal_rx_freqlocked_interconect),                     //           rx_freqlocked.interconect
		.test_in                (test_in_test_in),                                              //                 test_in.interconect
		.srst                   (reset_controller_internal_srst_interconect),                   //                    srst.interconect
		.crst                   (reset_controller_internal_crst_interconect),                   //                    crst.interconect
		.rx_digitalreset_serdes (reset_controller_internal_rx_digitalreset_serdes_interconect), //  rx_digitalreset_serdes.interconect
		.txdigitalreset         (reset_controller_internal_txdigitalreset_interconect),         //          txdigitalreset.interconect
		.rxanalogreset          (reset_controller_internal_rxanalogreset_interconect),          //           rxanalogreset.interconect
		.clk250_out             (reset_controller_internal_clk250_out_interconect),             //              clk250_out.interconect
		.clk500_out             (reset_controller_internal_clk500_out_interconect),             //              clk500_out.interconect
		.rc_inclk_eq_125mhz     (1'b1),                                                         //             (terminated)
		.rx_pll_locked          (1'b0),                                                         //             (terminated)
		.rx_signaldetect        (1'b0)                                                          //             (terminated)
	);

	altpcie_pipe_interface #(
		.max_link_width      (1),
		.gen2_lane_rate_mode ("false"),
		.p_pcie_hip_type     ("2")
	) pipe_interface_internal (
		.pipe_mode               (pipe_ext_pipe_mode),                                    //   pipe_interface_export.pipe_mode
		.phystatus_ext           (pipe_ext_phystatus_ext),                                //                        .phystatus_ext
		.rate_ext                (pipe_ext_rate_ext),                                     //                        .rate_ext
		.powerdown_ext           (pipe_ext_powerdown_ext),                                //                        .powerdown_ext
		.txdetectrx_ext          (pipe_ext_txdetectrx_ext),                               //                        .txdetectrx_ext
		.rxelecidle0_ext         (pipe_ext_rxelecidle0_ext),                              //                        .rxelecidle0_ext
		.rxdata0_ext             (pipe_ext_rxdata0_ext),                                  //                        .rxdata0_ext
		.rxstatus0_ext           (pipe_ext_rxstatus0_ext),                                //                        .rxstatus0_ext
		.rxvalid0_ext            (pipe_ext_rxvalid0_ext),                                 //                        .rxvalid0_ext
		.rxdatak0_ext            (pipe_ext_rxdatak0_ext),                                 //                        .rxdatak0_ext
		.txdata0_ext             (pipe_ext_txdata0_ext),                                  //                        .txdata0_ext
		.txdatak0_ext            (pipe_ext_txdatak0_ext),                                 //                        .txdatak0_ext
		.rxpolarity0_ext         (pipe_ext_rxpolarity0_ext),                              //                        .rxpolarity0_ext
		.txcompl0_ext            (pipe_ext_txcompl0_ext),                                 //                        .txcompl0_ext
		.txelecidle0_ext         (pipe_ext_txelecidle0_ext),                              //                        .txelecidle0_ext
		.pll_powerdown           (powerdown_pll_powerdown),                               //        powerdown_export.pll_powerdown
		.gxb_powerdown           (powerdown_gxb_powerdown),                               //                        .gxb_powerdown
		.pll_locked_pcs          (altgx_internal_pll_locked_interconect),                 //          pll_locked_pcs.interconect
		.hip_tx_clkout_pcs       (altgx_internal_hip_tx_clkout_0_interconect),            //       hip_tx_clkout_pcs.interconect
		.rate_hip                (pcie_internal_hip_rate_ext_interconect),                //                rate_hip.interconect
		.clk500_out              (reset_controller_internal_clk500_out_interconect),      //              clk500_out.interconect
		.clk250_out              (reset_controller_internal_clk250_out_interconect),      //              clk250_out.interconect
		.core_clk_out            (pcie_core_clk_clk),                                     //            core_clk_out.clk
		.rc_pll_locked           (pipe_interface_internal_rc_pll_locked_interconect),     //           rc_pll_locked.interconect
		.gxb_powerdown_pcs       (pipe_interface_internal_gxb_powerdown_pcs_interconect), //       gxb_powerdown_pcs.interconect
		.pll_powerdown_pcs       (),                                                      //       pll_powerdown_pcs.interconect
		.pclk_central_hip        (pipe_interface_internal_pclk_central_hip_interconect),  //        pclk_central_hip.interconect
		.pclk_ch0_hip            (pipe_interface_internal_pclk_ch0_hip_interconect),      //            pclk_ch0_hip.interconect
		.rateswitch_pcs          (),                                                      //          rateswitch_pcs.interconect
		.pll_fixed_clk_hip       (pipe_interface_internal_pll_fixed_clk_hip_interconect), //       pll_fixed_clk_hip.interconect
		.pcie_rstn               (pcie_rstn_export),                                      //               pcie_rstn.interconect
		.rc_areset               (pipe_interface_internal_rc_areset_interconect),         //               rc_areset.interconect
		.txdata0_hip             (pcie_internal_hip_txdata0_ext_interconect),             //             txdata0_hip.interconect
		.txdatak0_hip            (pcie_internal_hip_txdatak0_ext_interconect),            //            txdatak0_hip.interconect
		.powerdown0_hip          (pcie_internal_hip_powerdown0_ext_interconect),          //          powerdown0_hip.interconect
		.rxpolarity0_hip         (pcie_internal_hip_rxpolarity0_ext_interconect),         //         rxpolarity0_hip.interconect
		.txcompl0_hip            (pcie_internal_hip_txcompl0_ext_interconect),            //            txcompl0_hip.interconect
		.txdetectrx0_hip         (pcie_internal_hip_txdetectrx0_ext_interconect),         //         txdetectrx0_hip.interconect
		.txelecidle0_hip         (pcie_internal_hip_txelecidle0_ext_interconect),         //         txelecidle0_hip.interconect
		.rxdata_hip              (pipe_interface_internal_rxdata_hip),                    //            rxdata_hip_0.interconect
		.rxdatak_hip             (pipe_interface_internal_rxdatak_hip),                   //           rxdatak_hip_0.interconect
		.rxstatus_hip            (pipe_interface_internal_rxstatus_hip),                  //          rxstatus_hip_0.interconect
		.powerdown_pcs           (pipe_interface_internal_powerdown_pcs_interconect),     //           powerdown_pcs.interconect
		.rxdata_pcs              (altgx_internal_rx_dataout_interconect),                 //              rxdata_pcs.interconect
		.phystatus_pcs           (altgx_internal_pipephydonestatus_interconect),          //           phystatus_pcs.interconect
		.rxelecidle_pcs          (altgx_internal_pipeelecidle_interconect),               //          rxelecidle_pcs.interconect
		.rxvalid_pcs             (altgx_internal_pipedatavalid_interconect),              //             rxvalid_pcs.interconect
		.rxdatak_pcs             (altgx_internal_rx_ctrldetect_interconect),              //             rxdatak_pcs.interconect
		.rxstatus_pcs            (altgx_internal_pipestatus_interconect),                 //            rxstatus_pcs.interconect
		.txdata_pcs              (pipe_interface_internal_txdata_pcs_interconect),        //              txdata_pcs.interconect
		.rxpolarity_pcs          (pipe_interface_internal_rxpolarity_pcs_interconect),    //          rxpolarity_pcs.interconect
		.txcompl_pcs             (pipe_interface_internal_txcompl_pcs_interconect),       //             txcompl_pcs.interconect
		.txdatak_pcs             (pipe_interface_internal_txdatak_pcs_interconect),       //             txdatak_pcs.interconect
		.txdetectrx_pcs          (pipe_interface_internal_txdetectrx_pcs_interconect),    //          txdetectrx_pcs.interconect
		.txelecidle_pcs          (pipe_interface_internal_txelecidle_pcs_interconect),    //          txelecidle_pcs.interconect
		.phystatus_hip           (pipe_interface_internal_phystatus_hip),                 //         phystatus_hip_0.interconect
		.rxelecidle_hip          (pipe_interface_internal_rxelecidle_hip),                //        rxelecidle_hip_0.interconect
		.rxvalid_hip             (pipe_interface_internal_rxvalid_hip),                   //           rxvalid_hip_0.interconect
		.rateswitchbaseclock_pcs ()                                                       // rateswitchbaseclock_pcs.interconect
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("both"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~pcie_core_reset_reset_n),       // reset_in0.reset
		.clk        (pcie_core_clk_clk),              //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

	assign tx_out_tx_dataout_0 = { altgx_internal_tx_dataout[0] };

	assign pcie_internal_hip_dl_ltssm_int_interconect = { pcie_internal_hip_dl_ltssm[4:0] };

	assign altgx_internal_hip_tx_clkout_0_interconect = { altgx_internal_hip_tx_clkout[0] };

	assign pipe_interface_internal_rxdatak_hip_0_interconect = { pipe_interface_internal_rxdatak_hip[0] };

	assign pcie_internal_hip_eidle_infer_sel_0_interconect = { pcie_internal_hip_eidle_infer_sel[2:0] };

	assign pipe_interface_internal_rxdata_hip_0_interconect = { pipe_interface_internal_rxdata_hip[7:0] };

	assign pipe_interface_internal_rxvalid_hip_0_interconect = { pipe_interface_internal_rxvalid_hip[0] };

	assign pipe_interface_internal_rxelecidle_hip_0_interconect = { pipe_interface_internal_rxelecidle_hip[0] };

	assign pipe_interface_internal_phystatus_hip_0_interconect = { pipe_interface_internal_phystatus_hip[0] };

	assign pipe_interface_internal_rxstatus_hip_0_interconect = { pipe_interface_internal_rxstatus_hip[2:0] };

endmodule
