// megafunction wizard: %ALTGX_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb_reconfig 

// ============================================================
// File Name: altpcie_reconfig_4sgx.v
// Megafunction Name(s):
// 			alt2gxb_reconfig
//
// Simulation Library Files(s):
// 			
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Internal Build 215 05/06/2009 SP 2 SJ Full Version
// ************************************************************


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//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
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//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
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//applicable agreement for further details.


//alt2gxb_reconfig BASE_PORT_WIDTH=1 CBX_AUTO_BLACKBOX="ALL" CHANNEL_ADDRESS_WIDTH=3 DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" ENABLE_CHL_ADDR_FOR_ANALOG_CTRL="TRUE" NUMBER_OF_CHANNELS=8 NUMBER_OF_RECONFIG_PORTS=2 READ_BASE_PORT_WIDTH=1 RECONFIG_FROMGXB_WIDTH=34 RECONFIG_TOGXB_WIDTH=4 RX_EQDCGAIN_PORT_WIDTH=3 TX_PREEMP_PORT_WIDTH=5 busy data_valid logical_channel_address read reconfig_clk reconfig_fromgxb reconfig_mode_sel reconfig_togxb rx_eqctrl rx_eqctrl_out rx_eqdcgain rx_eqdcgain_out tx_preemp_0t tx_preemp_0t_out tx_preemp_1t tx_preemp_1t_out tx_preemp_2t tx_preemp_2t_out tx_vodctrl tx_vodctrl_out write_all
//VERSION_BEGIN 9.0SP2 cbx_alt2gxb_reconfig 2009:05:04:09:24:31:SJ cbx_alt_cal 2009:04:27:08:43:10:SJ cbx_alt_dprio 2008:07:22:18:38:30:SJ cbx_altsyncram 2009:04:03:15:10:30:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_lpm_shiftreg 2008:05:19:10:27:41:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=7 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden wren wren_data
//VERSION_BEGIN 9.0SP2 cbx_alt_dprio 2008:07:22:18:38:30:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_shiftreg 2008:05:19:10:27:41:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ  VERSION_END

//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
module  altpcie_reconfig_4sgx_alt_dprio_tcj
	( 
	address,
	busy,
	datain,
	dataout,
	dpclk,
	dpriodisable,
	dprioin,
	dprioload,
	dprioout,
	quad_address,
	rden,
	wren,
	wren_data) /* synthesis synthesis_clearbox=2 */;
	input   [15:0]  address;
	output   busy;
	input   [15:0]  datain;
	output   [15:0]  dataout;
	input   dpclk;
	output   dpriodisable;
	output   dprioin;
	output   dprioload;
	input   dprioout;
	input   [6:0]  quad_address;
	input   rden;
	input   wren;
	input   wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   [15:0]  datain;
	tri0   rden;
	tri0   wren;
	tri0   wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
	reg	[31:0]	addr_shift_reg;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
	reg	[15:0]	in_data_shift_reg;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
	reg	[15:0]	rd_out_data_shift_reg;
	wire	[2:0]	wire_startup_cntr_d;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
	reg	[2:0]	startup_cntr;
	wire	[2:0]	wire_startup_cntr_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[2:0]	state_mc_reg;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
	reg	[31:0]	wr_out_data_shift_reg;
	wire  wire_pre_amble_cmpr_aeb;
	wire  wire_pre_amble_cmpr_agb;
	wire  wire_rd_data_output_cmpr_ageb;
	wire  wire_rd_data_output_cmpr_alb;
	wire  wire_state_mc_cmpr_aeb;
	wire  [5:0]   wire_state_mc_counter_q;
	wire  [7:0]   wire_state_mc_decode_eq;
	wire	wire_dprioin_mux_dataout;
	wire  busy_state;
	wire  idle_state;
	wire  rd_addr_done;
	wire  rd_addr_state;
	wire  rd_data_done;
	wire  rd_data_input_state;
	wire  rd_data_output_state;
	wire  rd_data_state;
	wire rdinc;
	wire  read_state;
	wire  s0_to_0;
	wire  s0_to_1;
	wire  s1_to_0;
	wire  s1_to_1;
	wire  s2_to_0;
	wire  s2_to_1;
	wire  startup_done;
	wire  startup_idle;
	wire  wr_addr_done;
	wire  wr_addr_state;
	wire  wr_data_done;
	wire  wr_data_state;
	wire  write_state;

	// synopsys translate_off
	initial
		addr_shift_reg = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		
			if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, {3{1'b0}}, quad_address, 2'b10, address};
			else  addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
	// synopsys translate_off
	initial
		in_data_shift_reg = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		if (rd_data_input_state == 1'b1)   in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
	// synopsys translate_off
	initial
		rd_out_data_shift_reg = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		
			if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, {3{1'b0}}, quad_address, 2'b10};
			else  rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
	// synopsys translate_off
	initial
		startup_cntr[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		if (wire_startup_cntr_ena[0:0] == 1'b1)   startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
	// synopsys translate_off
	initial
		startup_cntr[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		if (wire_startup_cntr_ena[1:1] == 1'b1)   startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
	// synopsys translate_off
	initial
		startup_cntr[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		if (wire_startup_cntr_ena[2:2] == 1'b1)   startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
	assign
		wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
	assign
		wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
	// synopsys translate_off
	initial
		state_mc_reg = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		  state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
	// synopsys translate_off
	initial
		wr_out_data_shift_reg = 0;
	// synopsys translate_on
	always @ ( posedge dpclk)
		
			if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, {3{1'b0}}, quad_address, 2'b10, datain};
			else  wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
	lpm_compare   pre_amble_cmpr
	( 
	.aeb(wire_pre_amble_cmpr_aeb),
	.agb(wire_pre_amble_cmpr_agb),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(wire_state_mc_counter_q),
	.datab(6'b011111)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		pre_amble_cmpr.lpm_width = 6,
		pre_amble_cmpr.lpm_type = "lpm_compare";
	lpm_compare   rd_data_output_cmpr
	( 
	.aeb(),
	.agb(),
	.ageb(wire_rd_data_output_cmpr_ageb),
	.alb(wire_rd_data_output_cmpr_alb),
	.aleb(),
	.aneb(),
	.dataa(wire_state_mc_counter_q),
	.datab(6'b110000)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rd_data_output_cmpr.lpm_width = 6,
		rd_data_output_cmpr.lpm_type = "lpm_compare";
	lpm_compare   state_mc_cmpr
	( 
	.aeb(wire_state_mc_cmpr_aeb),
	.agb(),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(wire_state_mc_counter_q),
	.datab({6{1'b1}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		state_mc_cmpr.lpm_width = 6,
		state_mc_cmpr.lpm_type = "lpm_compare";
	lpm_counter   state_mc_counter
	( 
	.clock(dpclk),
	.cnt_en((write_state | read_state)),
	.cout(),
	.eq(),
	.q(wire_state_mc_counter_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.data({6{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		state_mc_counter.lpm_port_updown = "PORT_UNUSED",
		state_mc_counter.lpm_width = 6,
		state_mc_counter.lpm_type = "lpm_counter";
	lpm_decode   state_mc_decode
	( 
	.data(state_mc_reg),
	.eq(wire_state_mc_decode_eq)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0),
	.enable(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		state_mc_decode.lpm_decodes = 8,
		state_mc_decode.lpm_width = 3,
		state_mc_decode.lpm_type = "lpm_decode";
	or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
	assign
		busy = busy_state,
		busy_state = (write_state | read_state),
		dataout = in_data_shift_reg,
		dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
		dprioin = wire_dprioin_mux_dataout,
		dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
		idle_state = wire_state_mc_decode_eq[0],
		rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
		rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
		rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
		rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
		rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
		rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
		rdinc = 1'b0,
		read_state = (rd_addr_state | rd_data_state),
		s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
		s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
		s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
		s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
		s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
		s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
		startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
		startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
		wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
		wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
		wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
		wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
		write_state = (wr_addr_state | wr_data_state);
endmodule //altpcie_reconfig_4sgx_alt_dprio_tcj

//synthesis_resources = alt_cal 1 lpm_add_sub 4 lpm_compare 7 lpm_counter 4 lpm_decode 3 lpm_mux 2 lut 1 reg 146 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0"} *)
module  altpcie_reconfig_4sgx_alt2gxb_reconfig_77s1
	( 
	busy,
	data_valid,
	logical_channel_address,
	read,
	reconfig_clk,
	reconfig_fromgxb,
	reconfig_mode_sel,
	reconfig_togxb,
	rx_eqctrl,
	rx_eqctrl_out,
	rx_eqdcgain,
	rx_eqdcgain_out,
	tx_preemp_0t,
	tx_preemp_0t_out,
	tx_preemp_1t,
	tx_preemp_1t_out,
	tx_preemp_2t,
	tx_preemp_2t_out,
	tx_vodctrl,
	tx_vodctrl_out,
	write_all) /* synthesis synthesis_clearbox=2 */;
	output   busy;
	output   data_valid;
	input   [2:0]  logical_channel_address;
	input   read;
	input   reconfig_clk;
	input   [33:0]  reconfig_fromgxb;
	input   [2:0]  reconfig_mode_sel;
	output   [3:0]  reconfig_togxb;
	input   [3:0]  rx_eqctrl;
	output   [3:0]  rx_eqctrl_out;
	input   [2:0]  rx_eqdcgain;
	output   [2:0]  rx_eqdcgain_out;
	input   [4:0]  tx_preemp_0t;
	output   [4:0]  tx_preemp_0t_out;
	input   [4:0]  tx_preemp_1t;
	output   [4:0]  tx_preemp_1t_out;
	input   [4:0]  tx_preemp_2t;
	output   [4:0]  tx_preemp_2t_out;
	input   [2:0]  tx_vodctrl;
	output   [2:0]  tx_vodctrl_out;
	input   write_all;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   [2:0]  logical_channel_address;
	tri0   read;
	tri0   [2:0]  reconfig_mode_sel;
	tri0   [3:0]  rx_eqctrl;
	tri0   [2:0]  rx_eqdcgain;
	tri0   [4:0]  tx_preemp_0t;
	tri0   [4:0]  tx_preemp_1t;
	tri0   [4:0]  tx_preemp_2t;
	tri0   [2:0]  tx_vodctrl;
	tri0   write_all;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  wire_calibration_busy;
	wire  [15:0]   wire_calibration_dprio_addr;
	wire  [15:0]   wire_calibration_dprio_dataout;
	wire  wire_calibration_dprio_rden;
	wire  wire_calibration_dprio_wren;
	wire  [6:0]   wire_calibration_quad_addr;
	wire  [0:0]   wire_calibration_retain_addr;
	wire  wire_dprio_busy;
	wire  [15:0]   wire_dprio_dataout;
	wire  wire_dprio_dpriodisable;
	wire  wire_dprio_dprioin;
	wire  wire_dprio_dprioload;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
	reg	[9:0]	address_pres_reg;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	data_valid_reg;
	wire	wire_data_valid_reg_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dprio_pulse_reg;
	wire	wire_dprio_pulse_reg_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[2:0]	reconf_mode_sel_reg;
	wire	[3:0]	wire_rx_eqctrl_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[3:0]	rx_eqctrl_reg;
	wire	[3:0]	wire_rx_eqctrl_reg_ena;
	wire	[2:0]	wire_rx_equalizer_dcgain_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[2:0]	rx_equalizer_dcgain_reg;
	wire	[2:0]	wire_rx_equalizer_dcgain_reg_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[1:0]	state_mc_reg;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[0:0]	tx_preemp_0t_inv_reg;
	wire	wire_tx_preemp_0t_inv_reg_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[0:0]	tx_preemp_2t_inv_reg;
	wire	wire_tx_preemp_2t_inv_reg_ena;
	wire	[4:0]	wire_tx_preemphasisctrl_1stposttap_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[4:0]	tx_preemphasisctrl_1stposttap_reg;
	wire	[4:0]	wire_tx_preemphasisctrl_1stposttap_reg_ena;
	wire	[3:0]	wire_tx_preemphasisctrl_2ndposttap_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[3:0]	tx_preemphasisctrl_2ndposttap_reg;
	wire	[3:0]	wire_tx_preemphasisctrl_2ndposttap_reg_ena;
	wire	[3:0]	wire_tx_preemphasisctrl_pretap_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[3:0]	tx_preemphasisctrl_pretap_reg;
	wire	[3:0]	wire_tx_preemphasisctrl_pretap_reg_ena;
	wire	[2:0]	wire_tx_vodctrl_reg_d;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	[2:0]	tx_vodctrl_reg;
	wire	[2:0]	wire_tx_vodctrl_reg_ena;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	wr_addr_inc_reg;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	wr_rd_pulse_reg;
	wire	wire_wr_rd_pulse_reg_ena;
	wire	wire_wr_rd_pulse_reg_sclr;
	wire  [3:0]   wire_add_sub1_result;
	wire  [3:0]   wire_add_sub10_result;
	wire  [3:0]   wire_add_sub2_result;
	wire  [3:0]   wire_add_sub9_result;
	wire  wire_cmpr5_agb;
	wire  wire_cmpr6_agb;
	wire  wire_cmpr7_agb;
	wire  wire_cmpr8_agb;
	wire  [2:0]   wire_addr_cntr_q;
	wire  [2:0]   wire_read_addr_cntr_q;
	wire  [2:0]   wire_write_addr_cntr_q;
	wire  [7:0]   wire_chl_addr_decode_eq;
	wire  [7:0]   wire_reconf_mode_dec_eq;
	wire  [0:0]   wire_aeq_ch_done_mux_result;
	wire  [0:0]   wire_dprioout_mux_result;
	wire  [15:0]  a2gr_dprio_addr;
	wire  [15:0]  a2gr_dprio_data;
	wire  a2gr_dprio_rden;
	wire  a2gr_dprio_wren;
	wire  adce_busy_state;
	wire  adce_state;
	wire  [7:0]  aeq_ch_done;
	wire  busy_state;
	wire  cal_busy;
	wire  [2:0]  cal_channel_address;
	wire  [2:0]  cal_channel_address_out;
	wire  [15:0]  cal_dprio_address;
	wire  [1:0]  cal_dprioout_wire;
	wire  [6:0]  cal_quad_address;
	wire  [31:0]  cal_testbuses;
	wire  [1:0]  channel_address;
	wire  [1:0]  channel_address_out;
	wire  [15:0]  dprio_datain;
	wire  [15:0]  dprio_datain_64_67;
	wire  [15:0]  dprio_datain_68_6B;
	wire  [15:0]  dprio_datain_7c_7f;
	wire  [15:0]  dprio_datain_7c_7f_inv;
	wire  [15:0]  dprio_datain_preemp1t;
	wire  [15:0]  dprio_datain_vodctrl;
	wire  dprio_pulse;
	wire  en_read_trigger;
	wire  en_write_trigger;
	wire  header_proc;
	wire  idle_state;
	wire  illegal_rd_mode_type;
	wire  illegal_wr_mode_type;
	wire  internal_write_pulse;
	wire  is_adce;
	wire  is_adce_all_control;
	wire  is_adce_single_control;
	wire  is_analog_control;
	wire  is_cent_clk_div;
	wire  is_cmu_refsel;
	wire  is_cruclk_addr0;
	wire  is_illegal_reg_d;
	wire  is_illegal_reg_out;
	wire  is_rcxpat_chnl_en_ch;
	wire  is_tier_1;
	wire  is_tier_2;
	wire  is_tx_local_div_ctrl;
	wire  local_ch_dec;
	wire  mif_reconfig_done;
	wire  pll_address;
	wire  [1:0]  pll_sel_num;
	wire  [6:0]  quad_address;
	wire  [6:0]  quad_address_out;
	wire  rd_pulse;
	wire  read_addr_inc;
	wire  [15:0]  read_address;
	wire  read_done;
	wire  read_state;
	wire  read_word_64_67_data_valid;
	wire  read_word_68_6B_data_valid;
	wire  read_word_7c_7f_data_valid;
	wire  read_word_7c_7f_inv_data_valid;
	wire  read_word_done;
	wire  read_word_preemp_1t_data_valid;
	wire  read_word_vodctrl_data_valid;
	wire  [15:0]  reconfig_datain;
	wire  reset_reconf_addr;
	wire reset_reconfig_address;
	wire  reset_system;
	wire  rx_reconfig;
	wire  s0_to_0;
	wire  s0_to_1;
	wire  s0_to_2;
	wire  s1_to_0;
	wire  s1_to_1;
	wire  s2_to_0;
	wire  [1:0]  state_mc_reg_in;
	wire  [3:0]  tx_preemp_0t_out_wire;
	wire  [3:0]  tx_preemp_0t_wire;
	wire  [3:0]  tx_preemp_2t_out_wire;
	wire  [3:0]  tx_preemp_2t_wire;
	wire  tx_reconfig;
	wire  [8:0]  w263w;
	wire  [2:0]  w_rx_eqa460w;
	wire  [2:0]  w_rx_eqb459w;
	wire  [2:0]  w_rx_eqc458w;
	wire  [2:0]  w_rx_eqd457w;
	wire  [2:0]  w_rx_eqv461w;
	wire  wr_pulse;
	wire  write_addr_inc;
	wire  [15:0]  write_address;
	wire  write_all_int;
	wire  write_done;
	wire  write_happened;
	wire  write_skip;
	wire  write_state;
	wire  write_word_64_67_data_valid;
	wire  write_word_68_6B_data_valid;
	wire  write_word_7c_7f_data_valid;
	wire  write_word_7c_7f_inv_data_valid;
	wire  write_word_done;
	wire  write_word_preemp1t_data_valid;
	wire  write_word_vodctrl_data_valid;

	alt_cal   calibration
	( 
	.busy(wire_calibration_busy),
	.cal_error(),
	.clock(reconfig_clk),
	.dprio_addr(wire_calibration_dprio_addr),
	.dprio_busy(wire_dprio_busy),
	.dprio_datain(wire_dprio_dataout),
	.dprio_dataout(wire_calibration_dprio_dataout),
	.dprio_rden(wire_calibration_dprio_rden),
	.dprio_wren(wire_calibration_dprio_wren),
	.quad_addr(wire_calibration_quad_addr),
	.remap_addr(address_pres_reg),
	.reset(reset_reconfig_address),
	.retain_addr(wire_calibration_retain_addr),
	.testbuses(cal_testbuses)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.start(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		calibration.channel_address_width = 3,
		calibration.number_of_channels = 8,
		calibration.sim_model_mode = "FALSE",
		calibration.lpm_type = "alt_cal";
	altpcie_reconfig_4sgx_alt_dprio_tcj   dprio
	( 
	.address((({16{wire_calibration_busy}} & cal_dprio_address) | ({16{(~ wire_calibration_busy)}} & a2gr_dprio_addr))),
	.busy(wire_dprio_busy),
	.datain((({16{wire_calibration_busy}} & wire_calibration_dprio_dataout) | ({16{(~ wire_calibration_busy)}} & a2gr_dprio_data))),
	.dataout(wire_dprio_dataout),
	.dpclk(reconfig_clk),
	.dpriodisable(wire_dprio_dpriodisable),
	.dprioin(wire_dprio_dprioin),
	.dprioload(wire_dprio_dprioload),
	.dprioout(wire_dprioout_mux_result),
	.quad_address(quad_address_out),
	.rden(((wire_calibration_busy & wire_calibration_dprio_rden) | ((~ wire_calibration_busy) & a2gr_dprio_rden))),
	.wren(((wire_calibration_busy & wire_calibration_dprio_wren) | ((~ wire_calibration_busy) & a2gr_dprio_wren))),
	.wren_data(wire_calibration_retain_addr));
	// synopsys translate_off
	initial
		address_pres_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		  address_pres_reg <= {(({7{cal_busy}} & cal_quad_address) | ({7{(~ cal_busy)}} & quad_address)), ((cal_busy & cal_channel_address[2]) | ((~ cal_busy) & pll_address)), (({2{cal_busy}} & cal_channel_address[1:0]) | ({2{(~ cal_busy)}} & ((channel_address & {2{(~ pll_address)}}) | (pll_sel_num & {2{pll_address}}))))};
	// synopsys translate_off
	initial
		data_valid_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_data_valid_reg_ena == 1'b1)   data_valid_reg <= (~ (is_illegal_reg_out | reset_system));
	assign
		wire_data_valid_reg_ena = (read_state | write_state);
	// synopsys translate_off
	initial
		dprio_pulse_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_dprio_pulse_reg_ena == 1'b1)   dprio_pulse_reg <= wire_dprio_busy;
	assign
		wire_dprio_pulse_reg_ena = (read_state | write_state);
	// synopsys translate_off
	initial
		reconf_mode_sel_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		  reconf_mode_sel_reg <= reconfig_mode_sel;
	// synopsys translate_off
	initial
		rx_eqctrl_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_eqctrl_reg_ena[0:0] == 1'b1)   rx_eqctrl_reg[0:0] <= wire_rx_eqctrl_reg_d[0:0];
	// synopsys translate_off
	initial
		rx_eqctrl_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_eqctrl_reg_ena[1:1] == 1'b1)   rx_eqctrl_reg[1:1] <= wire_rx_eqctrl_reg_d[1:1];
	// synopsys translate_off
	initial
		rx_eqctrl_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_eqctrl_reg_ena[2:2] == 1'b1)   rx_eqctrl_reg[2:2] <= wire_rx_eqctrl_reg_d[2:2];
	// synopsys translate_off
	initial
		rx_eqctrl_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_eqctrl_reg_ena[3:3] == 1'b1)   rx_eqctrl_reg[3:3] <= wire_rx_eqctrl_reg_d[3:3];
	assign
		wire_rx_eqctrl_reg_d = (({4{read_state}} & (((({{2{1'b0}}, (w_rx_eqv461w[2] & (~ (w_rx_eqv461w[1] ^ w_rx_eqv461w[0]))), (((w_rx_eqv461w[2] & w_rx_eqv461w[1]) & w_rx_eqv461w[0]) | (((~ w_rx_eqv461w[2]) & (~ w_rx_eqv461w[1])) & (~ w_rx_eqv461w[0])))} & {4{(((((w_rx_eqd457w[2] & w_rx_eqd457w[1]) & w_rx_eqd457w[0]) & (~ ((w_rx_eqc458w[2] & w_rx_eqc458w[1]) & w_rx_eqc458w[0]))) & (~ ((w_rx_eqb459w[2] & w_rx_eqb459w[1]) & w_rx_eqb459w[0]))) & (~ ((w_rx_eqa460w[2] & w_rx_eqa460w[1]) & w_rx_eqa460w[0])))}}) | ({1'b0, 1'b1, ((w_rx_eqv461w[2] & w_rx_eqv461w[1]) & w_rx_eqv461w[0]), ((w_rx_eqv461w[2] & (~ w_rx_eqv461w[1])) & (~ w_rx_eqv461w[0]))} & {4{(((((w_rx_eqd457w[2] & w_rx_eqd457w[1]) & w_rx_eqd457w[0]) & ((w_rx_eqc458w[2] & w_rx_eqc458w[1]) & w_rx_eqc458w[0])) & (~ ((w_rx_eqb459w[2] & w_rx_eqb459w[1]) & w_rx_eqb459w[0]))) & (~ ((w_rx_eqa460w[2] & w_rx_eqa460w[1]) & w_rx_eqa460w[0])))}})) | ({w_rx_eqv461w[2], (~ w_rx_eqv461w[2]), (((w_rx_eqv461w[2] & w_rx_eqv461w[1]) & w_rx_eqv461w[0]) | (((~ w_rx_eqv461w[2]) & (~ w_rx_eqv461w[1])) & (~ w_rx_eqv461w[0]))), ((~ w_rx_eqv461w[1]) & (~ (w_rx_eqv461w[2] ^ w_rx_eqv461w[0])))} & {4{(((((w_rx_eqd457w[2] & w_rx_eqd457w[1]) & w_rx_eqd457w[0]) & ((w_rx_eqc458w[2] & w_rx_eqc458w[1]) & w_rx_eqc458w[0])) & ((w_rx_eqb459w[2] & w_rx_eqb459w[1]) & w_rx_eqb459w[0])) & (~ ((w_rx_eqa460w[2] & w_rx_eqa460w[1]) & w_rx_eqa460w[0])))}})) | ({1'b1, ((w_rx_eqv461w[2] | w_rx_eqv461w[1]) | w_rx_eqv461w[0]), (((~ w_rx_eqv461w[1]) & (~ (w_rx_eqv461w[2] ^ w_rx_eqv461w[0]))) | ((w_rx_eqv461w[2] & w_rx_eqv461w[1]) & w_rx_eqv461w[0])), (((~ w_rx_eqv461w[1]) & (~ w_rx_eqv461w[0])) | ((w_rx_eqv461w[2] & w_rx_eqv461w[1]) & w_rx_eqv461w[0]))} & {4{(((((w_rx_eqd457w[2] & w_rx_eqd457w[1]) & w_rx_eqd457w[0]) & ((w_rx_eqc458w[2] & w_rx_eqc458w[1]) & w_rx_eqc458w[0])) & ((w_rx_eqb459w[2] & w_rx_eqb459w[1]) & w_rx_eqb459w[0])) & ((w_rx_eqa460w[2] & w_rx_eqa460w[1]) & w_rx_eqa460w[0]))}}))) | ({4{write_state}} & rx_eqctrl));
	assign
		wire_rx_eqctrl_reg_ena = {4{((read_word_68_6B_data_valid & read_state) | (write_state & write_word_68_6B_data_valid))}};
	// synopsys translate_off
	initial
		rx_equalizer_dcgain_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_equalizer_dcgain_reg_ena[0:0] == 1'b1)   rx_equalizer_dcgain_reg[0:0] <= wire_rx_equalizer_dcgain_reg_d[0:0];
	// synopsys translate_off
	initial
		rx_equalizer_dcgain_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_equalizer_dcgain_reg_ena[1:1] == 1'b1)   rx_equalizer_dcgain_reg[1:1] <= wire_rx_equalizer_dcgain_reg_d[1:1];
	// synopsys translate_off
	initial
		rx_equalizer_dcgain_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_rx_equalizer_dcgain_reg_ena[2:2] == 1'b1)   rx_equalizer_dcgain_reg[2:2] <= wire_rx_equalizer_dcgain_reg_d[2:2];
	assign
		wire_rx_equalizer_dcgain_reg_d = (({3{read_state}} & {wire_dprio_dataout[10], (wire_dprio_dataout[8] & (~ wire_dprio_dataout[10])), (((wire_dprio_dataout[7] ^ wire_dprio_dataout[8]) ^ wire_dprio_dataout[9]) ^ wire_dprio_dataout[10])}) | ({3{write_state}} & rx_eqdcgain));
	assign
		wire_rx_equalizer_dcgain_reg_ena = {3{((read_word_64_67_data_valid & read_state) | (write_state & write_word_64_67_data_valid))}};
	// synopsys translate_off
	initial
		state_mc_reg = 2'b00;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		  state_mc_reg <= state_mc_reg_in;
	// synopsys translate_off
	initial
		tx_preemp_0t_inv_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemp_0t_inv_reg_ena == 1'b1)   tx_preemp_0t_inv_reg <= ((read_state & wire_dprio_dataout[4]) | (write_state & (~ tx_preemp_0t[4])));
	assign
		wire_tx_preemp_0t_inv_reg_ena = ((read_word_7c_7f_inv_data_valid & read_state) | (write_state & write_word_7c_7f_inv_data_valid));
	// synopsys translate_off
	initial
		tx_preemp_2t_inv_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemp_2t_inv_reg_ena == 1'b1)   tx_preemp_2t_inv_reg <= ((read_state & wire_dprio_dataout[3]) | (write_state & (~ tx_preemp_2t[4])));
	assign
		wire_tx_preemp_2t_inv_reg_ena = ((read_word_7c_7f_inv_data_valid & read_state) | (write_state & write_word_7c_7f_inv_data_valid));
	// synopsys translate_off
	initial
		tx_preemphasisctrl_1stposttap_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_1stposttap_reg_ena[0:0] == 1'b1)   tx_preemphasisctrl_1stposttap_reg[0:0] <= wire_tx_preemphasisctrl_1stposttap_reg_d[0:0];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_1stposttap_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_1stposttap_reg_ena[1:1] == 1'b1)   tx_preemphasisctrl_1stposttap_reg[1:1] <= wire_tx_preemphasisctrl_1stposttap_reg_d[1:1];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_1stposttap_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_1stposttap_reg_ena[2:2] == 1'b1)   tx_preemphasisctrl_1stposttap_reg[2:2] <= wire_tx_preemphasisctrl_1stposttap_reg_d[2:2];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_1stposttap_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_1stposttap_reg_ena[3:3] == 1'b1)   tx_preemphasisctrl_1stposttap_reg[3:3] <= wire_tx_preemphasisctrl_1stposttap_reg_d[3:3];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_1stposttap_reg[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_1stposttap_reg_ena[4:4] == 1'b1)   tx_preemphasisctrl_1stposttap_reg[4:4] <= wire_tx_preemphasisctrl_1stposttap_reg_d[4:4];
	assign
		wire_tx_preemphasisctrl_1stposttap_reg_d = (({5{read_state}} & wire_dprio_dataout[15:11]) | ({5{write_state}} & tx_preemp_1t));
	assign
		wire_tx_preemphasisctrl_1stposttap_reg_ena = {5{((read_word_preemp_1t_data_valid & read_state) | (write_state & write_word_preemp1t_data_valid))}};
	// synopsys translate_off
	initial
		tx_preemphasisctrl_2ndposttap_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[0:0] == 1'b1)   tx_preemphasisctrl_2ndposttap_reg[0:0] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[0:0];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_2ndposttap_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[1:1] == 1'b1)   tx_preemphasisctrl_2ndposttap_reg[1:1] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[1:1];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_2ndposttap_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[2:2] == 1'b1)   tx_preemphasisctrl_2ndposttap_reg[2:2] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[2:2];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_2ndposttap_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[3:3] == 1'b1)   tx_preemphasisctrl_2ndposttap_reg[3:3] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[3:3];
	assign
		wire_tx_preemphasisctrl_2ndposttap_reg_d = (({4{read_state}} & wire_dprio_dataout[7:4]) | ({4{write_state}} & tx_preemp_2t_wire[3:0]));
	assign
		wire_tx_preemphasisctrl_2ndposttap_reg_ena = {4{((read_word_7c_7f_data_valid & read_state) | (write_state & write_word_7c_7f_data_valid))}};
	// synopsys translate_off
	initial
		tx_preemphasisctrl_pretap_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_pretap_reg_ena[0:0] == 1'b1)   tx_preemphasisctrl_pretap_reg[0:0] <= wire_tx_preemphasisctrl_pretap_reg_d[0:0];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_pretap_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_pretap_reg_ena[1:1] == 1'b1)   tx_preemphasisctrl_pretap_reg[1:1] <= wire_tx_preemphasisctrl_pretap_reg_d[1:1];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_pretap_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_pretap_reg_ena[2:2] == 1'b1)   tx_preemphasisctrl_pretap_reg[2:2] <= wire_tx_preemphasisctrl_pretap_reg_d[2:2];
	// synopsys translate_off
	initial
		tx_preemphasisctrl_pretap_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_preemphasisctrl_pretap_reg_ena[3:3] == 1'b1)   tx_preemphasisctrl_pretap_reg[3:3] <= wire_tx_preemphasisctrl_pretap_reg_d[3:3];
	assign
		wire_tx_preemphasisctrl_pretap_reg_d = (({4{read_state}} & wire_dprio_dataout[3:0]) | ({4{write_state}} & tx_preemp_0t_wire[3:0]));
	assign
		wire_tx_preemphasisctrl_pretap_reg_ena = {4{((read_state & read_word_7c_7f_data_valid) | (write_state & write_word_7c_7f_data_valid))}};
	// synopsys translate_off
	initial
		tx_vodctrl_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_vodctrl_reg_ena[0:0] == 1'b1)   tx_vodctrl_reg[0:0] <= wire_tx_vodctrl_reg_d[0:0];
	// synopsys translate_off
	initial
		tx_vodctrl_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_vodctrl_reg_ena[1:1] == 1'b1)   tx_vodctrl_reg[1:1] <= wire_tx_vodctrl_reg_d[1:1];
	// synopsys translate_off
	initial
		tx_vodctrl_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_tx_vodctrl_reg_ena[2:2] == 1'b1)   tx_vodctrl_reg[2:2] <= wire_tx_vodctrl_reg_d[2:2];
	assign
		wire_tx_vodctrl_reg_d = (({3{read_state}} & {((wire_dprio_dataout[14] & wire_dprio_dataout[13]) | (wire_dprio_dataout[15] & (~ wire_dprio_dataout[14]))), ((wire_dprio_dataout[14] & (~ wire_dprio_dataout[13])) | (wire_dprio_dataout[15] & (~ wire_dprio_dataout[14]))), (((~ wire_dprio_dataout[14]) & wire_dprio_dataout[13]) | (wire_dprio_dataout[15] & wire_dprio_dataout[14]))}) | ({3{write_state}} & tx_vodctrl));
	assign
		wire_tx_vodctrl_reg_ena = {3{((read_word_vodctrl_data_valid & read_state) | (write_state & write_word_vodctrl_data_valid))}};
	// synopsys translate_off
	initial
		wr_addr_inc_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		  wr_addr_inc_reg <= (wr_pulse | (((~ wr_pulse) & (~ rd_pulse)) & wr_addr_inc_reg));
	// synopsys translate_off
	initial
		wr_rd_pulse_reg = 0;
	// synopsys translate_on
	always @ ( posedge reconfig_clk)
		if (wire_wr_rd_pulse_reg_ena == 1'b1) 
			if (wire_wr_rd_pulse_reg_sclr == 1'b1) wr_rd_pulse_reg <= 1'b0;
			else  wr_rd_pulse_reg <= (~ wr_rd_pulse_reg);
	assign
		wire_wr_rd_pulse_reg_ena = (dprio_pulse & (~ read_state)),
		wire_wr_rd_pulse_reg_sclr = (reset_system | (is_tier_1 & mif_reconfig_done));
	lpm_add_sub   add_sub1
	( 
	.add_sub(tx_preemp_0t[4]),
	.cout(),
	.dataa({4{1'b0}}),
	.datab(tx_preemp_0t[3:0]),
	.overflow(),
	.result(wire_add_sub1_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub1.lpm_width = 4,
		add_sub1.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub10
	( 
	.add_sub((~ tx_preemp_2t_inv_reg[0])),
	.cout(),
	.dataa({4{1'b0}}),
	.datab(tx_preemp_2t_out_wire[3:0]),
	.overflow(),
	.result(wire_add_sub10_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub10.lpm_width = 4,
		add_sub10.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub2
	( 
	.add_sub(tx_preemp_2t[4]),
	.cout(),
	.dataa({4{1'b0}}),
	.datab(tx_preemp_2t[3:0]),
	.overflow(),
	.result(wire_add_sub2_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub2.lpm_width = 4,
		add_sub2.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub9
	( 
	.add_sub((~ tx_preemp_0t_inv_reg[0])),
	.cout(),
	.dataa({4{1'b0}}),
	.datab(tx_preemp_0t_out_wire[3:0]),
	.overflow(),
	.result(wire_add_sub9_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub9.lpm_width = 4,
		add_sub9.lpm_type = "lpm_add_sub";
	lpm_compare   cmpr5
	( 
	.aeb(),
	.agb(wire_cmpr5_agb),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(rx_eqctrl[3:0]),
	.datab(4'b1010)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr5.lpm_width = 4,
		cmpr5.lpm_type = "lpm_compare";
	lpm_compare   cmpr6
	( 
	.aeb(),
	.agb(wire_cmpr6_agb),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(rx_eqctrl[3:0]),
	.datab(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr6.lpm_width = 4,
		cmpr6.lpm_type = "lpm_compare";
	lpm_compare   cmpr7
	( 
	.aeb(),
	.agb(wire_cmpr7_agb),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(rx_eqctrl[3:0]),
	.datab(4'b0011)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr7.lpm_width = 4,
		cmpr7.lpm_type = "lpm_compare";
	lpm_compare   cmpr8
	( 
	.aeb(),
	.agb(wire_cmpr8_agb),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa(rx_eqctrl[3:0]),
	.datab({4{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr8.lpm_width = 4,
		cmpr8.lpm_type = "lpm_compare";
	lpm_counter   addr_cntr
	( 
	.clock(reconfig_clk),
	.cnt_en(1'b0),
	.cout(),
	.data(logical_channel_address),
	.eq(),
	.q(wire_addr_cntr_q),
	.sclr(write_done),
	.sload((idle_state & (write_all | read)))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		addr_cntr.lpm_modulus = 8,
		addr_cntr.lpm_port_updown = "PORT_UNUSED",
		addr_cntr.lpm_width = 3,
		addr_cntr.lpm_type = "lpm_counter";
	lpm_counter   read_addr_cntr
	( 
	.clock(reconfig_clk),
	.cnt_en((read_addr_inc & is_analog_control)),
	.cout(),
	.data({1'b1, {2{1'b0}}}),
	.eq(),
	.q(wire_read_addr_cntr_q),
	.sclr((read_done | reset_system)),
	.sload(((idle_state & read) & (~ tx_reconfig)))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		read_addr_cntr.lpm_modulus = 6,
		read_addr_cntr.lpm_port_updown = "PORT_UNUSED",
		read_addr_cntr.lpm_width = 3,
		read_addr_cntr.lpm_type = "lpm_counter";
	lpm_counter   write_addr_cntr
	( 
	.clock(reconfig_clk),
	.cnt_en(write_addr_inc),
	.cout(),
	.data({1'b1, {2{1'b0}}}),
	.eq(),
	.q(wire_write_addr_cntr_q),
	.sclr((write_done | reset_system)),
	.sload(((idle_state & write_all) & (~ tx_reconfig)))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		write_addr_cntr.lpm_modulus = 6,
		write_addr_cntr.lpm_port_updown = "PORT_UNUSED",
		write_addr_cntr.lpm_width = 3,
		write_addr_cntr.lpm_type = "lpm_counter";
	lpm_decode   chl_addr_decode
	( 
	.data(wire_addr_cntr_q),
	.eq(wire_chl_addr_decode_eq)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0),
	.enable(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		chl_addr_decode.lpm_decodes = 8,
		chl_addr_decode.lpm_width = 3,
		chl_addr_decode.lpm_type = "lpm_decode";
	lpm_decode   reconf_mode_dec
	( 
	.data(reconf_mode_sel_reg),
	.eq(wire_reconf_mode_dec_eq)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0),
	.enable(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		reconf_mode_dec.lpm_decodes = 8,
		reconf_mode_dec.lpm_width = 3,
		reconf_mode_dec.lpm_type = "lpm_decode";
	lpm_mux   aeq_ch_done_mux
	( 
	.data(aeq_ch_done),
	.result(wire_aeq_ch_done_mux_result),
	.sel(w263w[2:0])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		aeq_ch_done_mux.lpm_size = 8,
		aeq_ch_done_mux.lpm_width = 1,
		aeq_ch_done_mux.lpm_widths = 3,
		aeq_ch_done_mux.lpm_type = "lpm_mux";
	lpm_mux   dprioout_mux
	( 
	.data(cal_dprioout_wire),
	.result(wire_dprioout_mux_result),
	.sel(((cal_busy & cal_quad_address[0]) | ((~ cal_busy) & quad_address[0])))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		dprioout_mux.lpm_size = 2,
		dprioout_mux.lpm_width = 1,
		dprioout_mux.lpm_widths = 1,
		dprioout_mux.lpm_type = "lpm_mux";
	assign
		a2gr_dprio_addr = ((write_address & {16{write_state}}) | (read_address & {16{read_state}})),
		a2gr_dprio_data = ((dprio_datain & {16{(~ header_proc)}}) & {16{write_state}}),
		a2gr_dprio_rden = rd_pulse,
		a2gr_dprio_wren = wr_pulse,
		adce_busy_state = 1'b0,
		adce_state = (state_mc_reg[0:0] & state_mc_reg[1:1]),
		aeq_ch_done = {8{1'b0}},
		busy = ((busy_state | internal_write_pulse) | cal_busy),
		busy_state = ((read_state | write_state) | adce_state),
		cal_busy = wire_calibration_busy,
		cal_channel_address = wire_calibration_dprio_addr[14:12],
		cal_channel_address_out = address_pres_reg[2:0],
		cal_dprio_address = {wire_calibration_dprio_addr[15], cal_channel_address_out, wire_calibration_dprio_addr[11:0]},
		cal_dprioout_wire = {reconfig_fromgxb[17], reconfig_fromgxb[0]},
		cal_quad_address = wire_calibration_quad_addr,
		cal_testbuses = {reconfig_fromgxb[33:18], reconfig_fromgxb[16:1]},
		channel_address = wire_addr_cntr_q[1:0],
		channel_address_out = address_pres_reg[1:0],
		data_valid = (data_valid_reg & idle_state),
		dprio_datain = ((((((((dprio_datain_vodctrl & {16{write_word_vodctrl_data_valid}}) | (dprio_datain_preemp1t & {16{write_word_preemp1t_data_valid}})) | (dprio_datain_64_67 & {16{write_word_64_67_data_valid}})) | ((dprio_datain_68_6B | {16{local_ch_dec}}) & {16{write_word_68_6B_data_valid}})) | (dprio_datain_7c_7f & {16{write_word_7c_7f_data_valid}})) | (dprio_datain_7c_7f_inv & {16{write_word_7c_7f_inv_data_valid}})) & {16{is_analog_control}}) | ({16{((is_tier_1 | is_tier_2) | is_tx_local_div_ctrl)}} & reconfig_datain)),
		dprio_datain_64_67 = {wire_dprio_dataout[15:11], {rx_eqdcgain[2], (rx_eqdcgain[2] | (rx_eqdcgain[1] & rx_eqdcgain[0])), (rx_eqdcgain[2] | rx_eqdcgain[1]), ((rx_eqdcgain[2] | rx_eqdcgain[1]) | rx_eqdcgain[0])}, wire_dprio_dataout[6:0]},
		dprio_datain_68_6B = {wire_dprio_dataout[15], {{3{wire_cmpr5_agb}}, {3{wire_cmpr6_agb}}, {3{wire_cmpr7_agb}}, {3{wire_cmpr8_agb}}, (((((rx_eqctrl[1] & (~ rx_eqctrl[0])) | (((~ rx_eqctrl[3]) & (~ rx_eqctrl[2])) & rx_eqctrl[1])) | ((rx_eqctrl[2] & (~ rx_eqctrl[1])) & rx_eqctrl[0])) | ((rx_eqctrl[3] & rx_eqctrl[2]) & rx_eqctrl[0])) | ((rx_eqctrl[3] & (~ rx_eqctrl[2])) & (~ rx_eqctrl[1]))), ((rx_eqctrl[1] & (rx_eqctrl[0] ^ (rx_eqctrl[2] ^ rx_eqctrl[3]))) | (((rx_eqctrl[3] & rx_eqctrl[2]) & (~ rx_eqctrl[1])) & (~ rx_eqctrl[0]))), (((((((~ (rx_eqctrl[3] ^ rx_eqctrl[2])) & rx_eqctrl[1]) & rx_eqctrl[0]) | ((rx_eqctrl[2] & rx_eqctrl[1]) & (~ rx_eqctrl[0]))) | ((rx_eqctrl[3] & rx_eqctrl[1]) & (~ rx_eqctrl[0]))) | ((rx_eqctrl[3] & rx_eqctrl[2]) & (~ rx_eqctrl[0]))) | (((rx_eqctrl[3] & (~ rx_eqctrl[2])) & (~ rx_eqctrl[1])) & rx_eqctrl[0]))}},
		dprio_datain_7c_7f = {wire_dprio_dataout[15:8], tx_preemp_2t_wire[3:0], tx_preemp_0t_wire[3:0]},
		dprio_datain_7c_7f_inv = {wire_dprio_dataout[15:5], (~ tx_preemp_0t[4]), (~ tx_preemp_2t[4]), wire_dprio_dataout[2:0]},
		dprio_datain_preemp1t = {tx_preemp_1t, wire_dprio_dataout[10:0]},
		dprio_datain_vodctrl = {{((tx_vodctrl[2] & tx_vodctrl[1]) | (tx_vodctrl[0] & (tx_vodctrl[2] ^ tx_vodctrl[1]))), (tx_vodctrl[2] ^ tx_vodctrl[1]), ((tx_vodctrl[2] & (~ tx_vodctrl[1])) | (tx_vodctrl[0] & (~ (tx_vodctrl[2] ^ tx_vodctrl[1]))))}, wire_dprio_dataout[12:0]},
		dprio_pulse = ((dprio_pulse_reg ^ wire_dprio_busy) & (~ wire_dprio_busy)),
		en_read_trigger = illegal_rd_mode_type,
		en_write_trigger = illegal_wr_mode_type,
		header_proc = 1'b0,
		idle_state = ((~ state_mc_reg[0:0]) & (~ state_mc_reg[1:1])),
		illegal_rd_mode_type = ((~ reconfig_mode_sel[2]) & ((~ reconfig_mode_sel[1]) & (~ reconfig_mode_sel[0]))),
		illegal_wr_mode_type = ((reconfig_mode_sel[2] & (~ (reconfig_mode_sel[1] & reconfig_mode_sel[0]))) | ((~ reconfig_mode_sel[2]) & (~ (reconfig_mode_sel[1] & (~ reconfig_mode_sel[0]))))),
		internal_write_pulse = 1'b0,
		is_adce = (is_adce_single_control | is_adce_all_control),
		is_adce_all_control = 1'b0,
		is_adce_single_control = 1'b0,
		is_analog_control = wire_reconf_mode_dec_eq[0],
		is_cent_clk_div = 1'b0,
		is_illegal_reg_d = 1'b0,
		is_illegal_reg_out = 1'b0,
		is_rcxpat_chnl_en_ch = 1'b0,
		is_tier_1 = 1'b0,
		is_tier_2 = 1'b0,
		is_tx_local_div_ctrl = 1'b0,
		local_ch_dec = wire_aeq_ch_done_mux_result,
		mif_reconfig_done = 1'b0,
		pll_address = 1'b0,
		quad_address = {{6{1'b0}}, wire_addr_cntr_q[2]},
		quad_address_out = address_pres_reg[9:3],
		rd_pulse = ((((((~ dprio_pulse) & (~ write_done)) & (~ wr_rd_pulse_reg)) & (write_state & (((~ header_proc) & (~ reset_reconf_addr)) & ((~ is_tier_1) | (is_tier_1 & (((is_rcxpat_chnl_en_ch | is_cruclk_addr0) | write_skip) | (is_cent_clk_div & (~ is_cmu_refsel)))))))) | ((read_state & (~ dprio_pulse)) & (~ read_done))) & (~ is_illegal_reg_d)),
		read_addr_inc = (read_state & dprio_pulse),
		read_address = {1'b0, address_pres_reg[2], channel_address_out, 1'b1, wire_read_addr_cntr_q[2], {6{1'b0}}, (wire_read_addr_cntr_q[2] & wire_read_addr_cntr_q[0]), 1'b0, (wire_read_addr_cntr_q[1] | (wire_read_addr_cntr_q[0] & wire_read_addr_cntr_q[2])), wire_read_addr_cntr_q[0]},
		read_done = (((read_word_done & read_addr_inc) | (is_illegal_reg_out & read_state)) | reset_system),
		read_state = (state_mc_reg[0:0] & (~ state_mc_reg[1:1])),
		read_word_64_67_data_valid = (((dprio_pulse & wire_read_addr_cntr_q[2]) & (~ wire_read_addr_cntr_q[1])) & (~ wire_read_addr_cntr_q[0])),
		read_word_68_6B_data_valid = (((dprio_pulse & wire_read_addr_cntr_q[2]) & (~ wire_read_addr_cntr_q[1])) & wire_read_addr_cntr_q[0]),
		read_word_7c_7f_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & wire_read_addr_cntr_q[1]) & (~ wire_read_addr_cntr_q[0])),
		read_word_7c_7f_inv_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & wire_read_addr_cntr_q[1]) & wire_read_addr_cntr_q[0]),
		read_word_done = ((read_word_68_6B_data_valid & rx_reconfig) | (read_word_7c_7f_inv_data_valid & (~ rx_reconfig))),
		read_word_preemp_1t_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & (~ wire_read_addr_cntr_q[1])) & wire_read_addr_cntr_q[0]),
		read_word_vodctrl_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & (~ wire_read_addr_cntr_q[1])) & (~ wire_read_addr_cntr_q[0])),
		reconfig_datain = {16{1'b0}},
		reconfig_togxb = {wire_calibration_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin},
		reset_reconf_addr = 1'b0,
		reset_reconfig_address = 1'b0,
		reset_system = 1'b0,
		rx_eqctrl_out = rx_eqctrl_reg,
		rx_eqdcgain_out = rx_equalizer_dcgain_reg,
		rx_reconfig = 1'b1,
		s0_to_0 = ((idle_state & write_all_int) | read_done),
		s0_to_1 = (((idle_state & (read & en_read_trigger)) & (~ write_state)) & (~ write_all_int)),
		s0_to_2 = ((idle_state & is_adce) & write_all),
		s1_to_0 = (((idle_state & (read & en_read_trigger)) & (~ write_state)) | write_done),
		s1_to_1 = (idle_state & write_all_int),
		s2_to_0 = (adce_state & (~ adce_busy_state)),
		state_mc_reg_in = {((s0_to_2 | s1_to_1) | ((((~ s2_to_0) & (~ s1_to_1)) & (~ s1_to_0)) & state_mc_reg[1])), ((s0_to_2 | s0_to_1) | ((((~ s2_to_0) & (~ s0_to_1)) & (~ s0_to_0)) & state_mc_reg[0]))},
		tx_preemp_0t_out = {(~ tx_preemp_0t_inv_reg[0]), wire_add_sub9_result},
		tx_preemp_0t_out_wire = tx_preemphasisctrl_pretap_reg,
		tx_preemp_0t_wire = wire_add_sub1_result,
		tx_preemp_1t_out = tx_preemphasisctrl_1stposttap_reg,
		tx_preemp_2t_out = {(~ tx_preemp_2t_inv_reg[0]), wire_add_sub10_result},
		tx_preemp_2t_out_wire = tx_preemphasisctrl_2ndposttap_reg,
		tx_preemp_2t_wire = wire_add_sub2_result,
		tx_reconfig = 1'b1,
		tx_vodctrl_out = tx_vodctrl_reg,
		w263w = {quad_address, channel_address},
		w_rx_eqa460w = wire_dprio_dataout[14:12],
		w_rx_eqb459w = wire_dprio_dataout[11:9],
		w_rx_eqc458w = wire_dprio_dataout[8:6],
		w_rx_eqd457w = wire_dprio_dataout[5:3],
		w_rx_eqv461w = wire_dprio_dataout[2:0],
		wr_pulse = ((((write_state & (~ dprio_pulse)) & (~ write_done)) & ((wr_rd_pulse_reg & ((~ is_tier_1) | ((is_tier_1 & (~ header_proc)) & (((is_rcxpat_chnl_en_ch | is_cruclk_addr0) | write_skip) | (is_cent_clk_div & (~ is_cmu_refsel)))))) | ((is_tier_1 & (~ header_proc)) & ((((~ is_rcxpat_chnl_en_ch) & (~ is_cruclk_addr0)) & (~ write_skip)) & (~ (is_cent_clk_div & (~ is_cmu_refsel))))))) & (~ is_illegal_reg_d)),
		write_addr_inc = ((write_state & dprio_pulse) & write_happened),
		write_address = {1'b0, address_pres_reg[2], channel_address_out, 1'b1, wire_write_addr_cntr_q[2], {6{1'b0}}, (wire_write_addr_cntr_q[2] & wire_write_addr_cntr_q[0]), 1'b0, (wire_write_addr_cntr_q[1] | (wire_write_addr_cntr_q[0] & wire_write_addr_cntr_q[2])), wire_write_addr_cntr_q[0]},
		write_all_int = (write_all & en_write_trigger),
		write_done = ((((write_word_done & write_addr_inc) & write_happened) | (is_illegal_reg_out & write_state)) | reset_system),
		write_happened = wr_addr_inc_reg,
		write_state = ((~ state_mc_reg[0:0]) & state_mc_reg[1:1]),
		write_word_64_67_data_valid = ((wire_write_addr_cntr_q[2] & (~ wire_write_addr_cntr_q[1])) & (~ wire_write_addr_cntr_q[0])),
		write_word_68_6B_data_valid = ((wire_write_addr_cntr_q[2] & (~ wire_write_addr_cntr_q[1])) & wire_write_addr_cntr_q[0]),
		write_word_7c_7f_data_valid = (((~ wire_write_addr_cntr_q[2]) & wire_write_addr_cntr_q[1]) & (~ wire_write_addr_cntr_q[0])),
		write_word_7c_7f_inv_data_valid = (((~ wire_write_addr_cntr_q[2]) & wire_write_addr_cntr_q[1]) & wire_write_addr_cntr_q[0]),
		write_word_done = (dprio_pulse & ((write_word_68_6B_data_valid & rx_reconfig) | (write_word_7c_7f_inv_data_valid & (~ rx_reconfig)))),
		write_word_preemp1t_data_valid = (((~ wire_write_addr_cntr_q[2]) & (~ wire_write_addr_cntr_q[1])) & wire_write_addr_cntr_q[0]),
		write_word_vodctrl_data_valid = (((~ wire_write_addr_cntr_q[2]) & (~ wire_write_addr_cntr_q[1])) & (~ wire_write_addr_cntr_q[0]));
endmodule //altpcie_reconfig_4sgx_alt2gxb_reconfig_77s1
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_reconfig_4sgx (
	logical_channel_address,
	read,
	reconfig_clk,
	reconfig_fromgxb,
	rx_eqctrl,
	rx_eqdcgain,
	tx_preemp_0t,
	tx_preemp_1t,
	tx_preemp_2t,
	tx_vodctrl,
	write_all,
	busy,
	data_valid,
	reconfig_togxb,
	rx_eqctrl_out,
	rx_eqdcgain_out,
	tx_preemp_0t_out,
	tx_preemp_1t_out,
	tx_preemp_2t_out,
	tx_vodctrl_out)/* synthesis synthesis_clearbox = 2 */;

	input	[2:0]  logical_channel_address;
	input	  read;
	input	  reconfig_clk;
	input	[33:0]  reconfig_fromgxb;
	input	[3:0]  rx_eqctrl;
	input	[2:0]  rx_eqdcgain;
	input	[4:0]  tx_preemp_0t;
	input	[4:0]  tx_preemp_1t;
	input	[4:0]  tx_preemp_2t;
	input	[2:0]  tx_vodctrl;
	input	  write_all;
	output	  busy;
	output	  data_valid;
	output	[3:0]  reconfig_togxb;
	output	[3:0]  rx_eqctrl_out;
	output	[2:0]  rx_eqdcgain_out;
	output	[4:0]  tx_preemp_0t_out;
	output	[4:0]  tx_preemp_1t_out;
	output	[4:0]  tx_preemp_2t_out;
	output	[2:0]  tx_vodctrl_out;

	wire [2:0] sub_wire0;
	wire [4:0] sub_wire1;
	wire [4:0] sub_wire2;
	wire  sub_wire3;
	wire [3:0] sub_wire4;
	wire [4:0] sub_wire5;
	wire [3:0] sub_wire6;
	wire  sub_wire7;
	wire [2:0] sub_wire8;
	wire [2:0] sub_wire9 = 3'h0;
	wire [2:0] rx_eqdcgain_out = sub_wire0[2:0];
	wire [4:0] tx_preemp_2t_out = sub_wire1[4:0];
	wire [4:0] tx_preemp_1t_out = sub_wire2[4:0];
	wire  busy = sub_wire3;
	wire [3:0] rx_eqctrl_out = sub_wire4[3:0];
	wire [4:0] tx_preemp_0t_out = sub_wire5[4:0];
	wire [3:0] reconfig_togxb = sub_wire6[3:0];
	wire  data_valid = sub_wire7;
	wire [2:0] tx_vodctrl_out = sub_wire8[2:0];

	altpcie_reconfig_4sgx_alt2gxb_reconfig_77s1	altpcie_reconfig_4sgx_alt2gxb_reconfig_77s1_component (
				.write_all (write_all),
				.tx_preemp_2t (tx_preemp_2t),
				.tx_preemp_1t (tx_preemp_1t),
				.tx_preemp_0t (tx_preemp_0t),
				.tx_vodctrl (tx_vodctrl),
				.read (read),
				.reconfig_mode_sel (sub_wire9),
				.logical_channel_address (logical_channel_address),
				.rx_eqdcgain (rx_eqdcgain),
				.reconfig_clk (reconfig_clk),
				.rx_eqctrl (rx_eqctrl),
				.reconfig_fromgxb (reconfig_fromgxb),
				.rx_eqdcgain_out (sub_wire0),
				.tx_preemp_2t_out (sub_wire1),
				.tx_preemp_1t_out (sub_wire2),
				.busy (sub_wire3),
				.rx_eqctrl_out (sub_wire4),
				.tx_preemp_0t_out (sub_wire5),
				.reconfig_togxb (sub_wire6),
				.data_valid (sub_wire7),
				.tx_vodctrl_out (sub_wire8))/* synthesis synthesis_clearbox=2
	 clearbox_macroname = alt2gxb_reconfig
	 clearbox_defparam = "base_port_width=1;channel_address_width=3;enable_chl_addr_for_analog_ctrl=TRUE;intended_device_family=Stratix IV;number_of_channels=8;number_of_reconfig_ports=2;read_base_port_width=1;rx_eqdcgain_port_width=3;tx_preemp_port_width=5;enable_buf_cal=true;reconfig_fromgxb_width=34;reconfig_togxb_width=4;" */;

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADCE NUMERIC "0"
// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: PMA NUMERIC "1"
// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: CHANNEL_ADDRESS_WIDTH NUMERIC "3"
// Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "2"
// Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_EQDCGAIN_PORT_WIDTH NUMERIC "3"
// Retrieval info: CONSTANT: TX_PREEMP_PORT_WIDTH NUMERIC "5"
// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "34"
// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
// Retrieval info: USED_PORT: @reconfig_mode_sel 0 0 3 0 INPUT NODEFVAL @reconfig_mode_sel[2..0]
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL busy
// Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL data_valid
// Retrieval info: USED_PORT: logical_channel_address 0 0 3 0 INPUT NODEFVAL logical_channel_address[2..0]
// Retrieval info: USED_PORT: read 0 0 0 0 INPUT NODEFVAL read
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL reconfig_clk
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 INPUT NODEFVAL reconfig_fromgxb[33..0]
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL reconfig_togxb[3..0]
// Retrieval info: USED_PORT: rx_eqctrl 0 0 4 0 INPUT NODEFVAL rx_eqctrl[3..0]
// Retrieval info: USED_PORT: rx_eqctrl_out 0 0 4 0 OUTPUT NODEFVAL rx_eqctrl_out[3..0]
// Retrieval info: USED_PORT: rx_eqdcgain 0 0 3 0 INPUT NODEFVAL rx_eqdcgain[2..0]
// Retrieval info: USED_PORT: rx_eqdcgain_out 0 0 3 0 OUTPUT NODEFVAL rx_eqdcgain_out[2..0]
// Retrieval info: USED_PORT: tx_preemp_0t 0 0 5 0 INPUT NODEFVAL tx_preemp_0t[4..0]
// Retrieval info: USED_PORT: tx_preemp_0t_out 0 0 5 0 OUTPUT NODEFVAL tx_preemp_0t_out[4..0]
// Retrieval info: USED_PORT: tx_preemp_1t 0 0 5 0 INPUT NODEFVAL tx_preemp_1t[4..0]
// Retrieval info: USED_PORT: tx_preemp_1t_out 0 0 5 0 OUTPUT NODEFVAL tx_preemp_1t_out[4..0]
// Retrieval info: USED_PORT: tx_preemp_2t 0 0 5 0 INPUT NODEFVAL tx_preemp_2t[4..0]
// Retrieval info: USED_PORT: tx_preemp_2t_out 0 0 5 0 OUTPUT NODEFVAL tx_preemp_2t_out[4..0]
// Retrieval info: USED_PORT: tx_vodctrl 0 0 3 0 INPUT NODEFVAL tx_vodctrl[2..0]
// Retrieval info: USED_PORT: tx_vodctrl_out 0 0 3 0 OUTPUT NODEFVAL tx_vodctrl_out[2..0]
// Retrieval info: USED_PORT: write_all 0 0 0 0 INPUT NODEFVAL write_all
// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 34 0 reconfig_fromgxb 0 0 34 0
// Retrieval info: CONNECT: @logical_channel_address 0 0 3 0 logical_channel_address 0 0 3 0
// Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
// Retrieval info: CONNECT: @read 0 0 0 0 read 0 0 0 0
// Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
// Retrieval info: CONNECT: @write_all 0 0 0 0 write_all 0 0 0 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: @tx_vodctrl 0 0 3 0 tx_vodctrl 0 0 3 0
// Retrieval info: CONNECT: tx_vodctrl_out 0 0 3 0 @tx_vodctrl_out 0 0 3 0
// Retrieval info: CONNECT: @tx_preemp_0t 0 0 5 0 tx_preemp_0t 0 0 5 0
// Retrieval info: CONNECT: tx_preemp_0t_out 0 0 5 0 @tx_preemp_0t_out 0 0 5 0
// Retrieval info: CONNECT: @tx_preemp_1t 0 0 5 0 tx_preemp_1t 0 0 5 0
// Retrieval info: CONNECT: tx_preemp_1t_out 0 0 5 0 @tx_preemp_1t_out 0 0 5 0
// Retrieval info: CONNECT: @tx_preemp_2t 0 0 5 0 tx_preemp_2t 0 0 5 0
// Retrieval info: CONNECT: tx_preemp_2t_out 0 0 5 0 @tx_preemp_2t_out 0 0 5 0
// Retrieval info: CONNECT: @rx_eqdcgain 0 0 3 0 rx_eqdcgain 0 0 3 0
// Retrieval info: CONNECT: rx_eqdcgain_out 0 0 3 0 @rx_eqdcgain_out 0 0 3 0
// Retrieval info: CONNECT: @rx_eqctrl 0 0 4 0 rx_eqctrl 0 0 4 0
// Retrieval info: CONNECT: rx_eqctrl_out 0 0 4 0 @rx_eqctrl_out 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx_bb.v FALSE
